Light-emitting diode, method for making light-emitting diode, integrated light-emitting diode and method for making integrated light-emitting diode, method for growing a nitride-based iii-v group compound semiconductor, light source cell unit, light-emitting diode backlight, and light-emitting diode display and electronic device

ABSTRACT

A light-emitting diode with (a) a substrate having at least one recessed portion on one main surface; (b) a sixth nitride-based III-V group compound semiconductor layer grown on the substrate without forming a space in the recessed portion; and (c) a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type formed over the sixth nitride-based III-V group compound semiconductor layer, wherein, a dislocation occurring, in the sixth nitride-based III-V group compound semiconductor layer, from an interface with a bottom surface of the recessed portion in a direction vertical to the one main surface arrives at an inclined face or its vicinity of a triangle having the bottom surface of the recessed portion as a base and bends in a direction parallel to the one main surface.

RELATED APPLICATION DATA

This application is a division of U.S. patent application Ser. No.11/383,526, filed May 16, 2006, the entirety of which is incorporatedherein by reference to the extent permitted by law. The presentapplication claims the benefit of priority to JP 2005-142462 filed inthe Japanese Patent Office on May 16, 2005, and Japanese PatentApplication JP 2006-105647 filed in the Japanese Patent Office on Apr.6, 2006, the entirety both of which are incorporated by reference hereinto the extent permitted by law.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a light-emitting diode and a method for makingsame, and also to an integrated light-emitting diode and a method formaking same. The present invention also relates to a method for growinga nitride-based III-IV group compound semiconductor, and a light sourcecell unit, a light-emitting diode backlight, a light-emitting diodedisplay and an electronic device using such a light-emitting diode asmentioned above. More particularly, the present invention relates to alight-emitting diode using a nitride-based III-V group compoundsemiconductor and a variety of devices or units using the light-emittingdiode.

2. Description of Related Art

In case where a GaN semiconductor is epitaxially grown on a differenttype of substrate such as a sapphire substrate, crystal defects,particularly, threading dislocations, occur in high density owing to agreat difference between lattice constants or thermal expansioncoefficients thereof.

To avoid this, a dislocation density reducing technique using selectivelateral growth has been hitherto widely used. According to thistechnique, a GaN semiconductor is epitaxially grown on a sapphiresubstrate or the like, after which the substrate is removed from acrystal growing apparatus. A growth mask made of a SiO₂ film or the likeis formed over the GaN semiconductor layer, followed by returning thesubstrate to the crystal growing apparatus wherein a GaN semiconductoris again epitaxially grown by use of the growth mask.

Although this technique ensures reduction of a dislocation density inthe upper GaN semiconductor layer, two cycles of the epitaxially growingcycles are needed, resulting in an increased cost.

To cope with this, there has been proposed a method wherein a dissimilarsubstrate is beforehand processed to provide a patterned indentedsurface, and a GaN semiconductor is epitaxially grown on the thusprocessed substrate (see, for example, Report of Mitsubishi CableIndustries, LTD., No. 98, October, 2001, entitled “Developments ofHigh-power UV LED Using A LEPS Technique” and Japanese Patent Laid-openNos. 2004-6931 and 2004-6937). This method is schematically shown inFIGS. 36A to 36C. As shown in FIG. 36A, a c-sapphire substrate 101 isprocessed to provide a patterned indented surface on one main surfacethereof. Reference numeral 101 a indicates a recessed portion andreference numeral 101 b indicates a protruded portion. These recessedportions 101 a and protruded portions 101 b extend along the <1-100>direction of the sapphire substrate. Next, a GaN semiconductor 102 isgrown on the sapphire substrate 101, for example, through the steps ofFIGS. 36B and 36C. In FIG. 36C, dotted lines indicate a growth interfaceon the way of growth. It is characteristic of this method that as shownin FIG. 36C, for example, a space 103 is formed between the sapphiresubstrate 101 and the GaN semiconductor layer 102 in each recessedportion 101 a. FIG. 37 schematically shows a crystal defect distributionin the GaN semiconductor layer 102 grown according to this method. Asshown in FIG. 37, threading dislocations 104 occur at a portion of theGaN semiconductor layer 102 above each protruded portion 101 b in adirection vertical to an interface with an upper face of the protrudedportion 101 b to form a defect density region 105. On the other hand, aportion located above the recessed portion 101 a and between adjacenthigh defect density regions 105 becomes a low defect density region 106.

It will be noted that in FIG. 36C, the buried form of the GaNsemiconductor layer 102 beneath the space 103 formed within the recess101 a of the sapphire substrate 101 is rectangular in shape. This buriedform may be triangular in some case. In this case, the GaN semiconductorlayer 102 buried inside the recessed portion 101 a contacts with the GaNsemiconductor layer 102 grown laterally from the protruded portion 101 bthereby forming a space, like the case of the rectangular form.

For reference, there is shown, in FIGS. 38A to 38D, how a GaNsemiconductor layer 102 is grown in case where the direction ofextension of the recessed portions 101 a and the protruded portions 101b is a <11-20> direction intersecting at right angles with a <1-100>direction of the sapphire substrate 101.

FIGS. 39A to 39F schematically show another growing method in relatedart, different from the above-mentioned one (see, for example, JapanesePatent Laid-open No. 2003-318441). As shown in FIG. 39A, using asapphire substrate 101 processed to have a patterned indented surface, aGaN semiconductor layer 102 is grown on the substrate through the stepsshown in FIGS. 39B to 39F. It is stated that according to this method,the GaN semiconductor layer 102 is grown without forming a space betweenthe sapphire substrate 101 and the GaN semiconductor layer 102.

SUMMARY OF THE INVENTION

With the growing method in related art shown in FIGS. 36A to 36C, thespace 103 between the sapphire substrate 101 and the GaN semiconductorlayer 102 is formed as set out above. According to the test resultsconducted by the inventors, where a light-emitting diode structure isformed by growing a GaN semiconductor layer on the GaN semiconductorlayer 102, there arises a problem in that an emission efficiency of thelight-emitting diode is low. This is considered as follows: lightemitted from the active layer upon operation of the light-emitting diodeis repeatedly reflected inside the space 103, thereby absorbing light toworsen a light extraction efficiency.

On the other hand, with another growth method in related art shown inFIGS. 39A to 39F, it is stated that no space is formed between thesapphire substrate 101 and the GaN semiconductor layer 102. However, itis considered difficult to reduce a dislocation density of the GaNsemiconductor layer 102 to a level similar to that of the growth methodin related art shown in FIGS. 36A to 36C. This leads to the fact thatwhere a light-emitting diode structure is used by growing a GaNsemiconductor layer on the GaN semiconductor layer 102 of a highdislocation density, these GaN semiconductor layers also increase indislocation density, thereby inviting a lowering of light-emittingefficiency.

It is desirable to provide a light-emitting diode that is remarkablyimproved in light extraction efficiency by solving the problem on theformation of such a space as discussed above, is significantly improvedin crystallinity of a nitride-based III-V group compound semiconductorlayer of the light-emitting diode thereby resulting in a very highlight-emitting efficiency, and can be manufactured at low costs by oneepitaxial growth and also to provide a method for making the diode of atype mentioned above.

It is also desirable to provide an integrated light-emitting diodehaving such advantages as mentioned above and a method for making same.

It is further desirable to provide a method for growing a nitride-basedIII-V compound semiconductor suitably used to manufacture such alight-emitting diode or integrated light-emitting diode.

It is a still further desirable to provide a variety of high-performancedevices, such as a light source cell unit, a light-emitting diodebacklight, a light-emitting diode display and other electronic devices,using such a light-emitting diode as mentioned above.

Other features of the present invention will become apparent from thefollowing description with reference to the accompanying drawings.

A number of embodiments of the present invention are summarized below.

According to a first embodiment of the present invention, there isprovided a method for making a light-emitting diode, which including thesteps of: providing a substrate having at least one recessed portion onone main surface thereof and growing a first nitride-based III-V groupcompound semiconductor layer through a state of making a triangle insection having a bottom surface of the recessed portion as a basethereof thereby burying the recessed portion; laterally growing a secondnitride-based III-V group compound semiconductor layer from the firstnitride-based III-V compound semiconductor layer over the substrate; andsuccessively growing a third nitride-based III-V group compoundsemiconductor layer of a first conduction type, an active layer and afourth nitride-based III-V group compound semiconductor layer of asecond conduction type on the second nitride-based III-V group compoundsemiconductor layer.

The first nitride-based III-V group semiconductor layer and the secondnitride-based III-V group semiconductor layer may be either type ofconduction and may be any of p, n and i types, and may be of the sameconduction type or of other conduction types from each other. Inaddition, two or more portions of different types may be mixed in thefirst nitride-based III-V group compound semiconductor layer or secondnitride-based III-V compound semiconductor layer.

Typically, when the first nitride-based III-V group compoundsemiconductor layer is grown, a dislocation occurs from an interfacewith the bottom surface of the recessed portion of the substrate in adirection vertical to one main surface of the substrate. When thisdislocation arrives at an inclined face or its vicinity of the firstnitride-based III-V group compound semiconductor layer in such a stateas to form a triangle in section, it bends so as to be kept away fromthe triangular portion in parallel to the one main surface. Alsotypically, when the first nitride-based III-V group compoundsemiconductor layer and the second nitride-based III-V group compoundsemiconductor layer are, respectively, grown, a first pit having a firstwidth is formed in the substrate at a bottom of the recessed portionthereof and a second pit having a second width larger than the firstwidth is formed in the substrate at the opposite sides of the recessedportion. These first and second pits are formed by reflection of thegrowth of the first nitride-based III-V group compound semiconductorlayer and the second nitride-based III-V group compound semiconductorlayer in such a way as set out above. Typically, recessed portions andprotruded portions should be alternately arranged on the one surface ofthe substrate. The recessed portion may be formed as extended in astriped form in one direction, or may be extended in striped forms infirst and second directions, at least, intersecting with each otherthereby providing a two-dimensional pattern where a protruded portion isin the form of a triangle, a quadrangle, a pentagon, a hexagon or thelike with corners being cut off or rounded, or in the form of a circle,an ellipse, dots or the like. In one preferred instance, the protrudedportion has a hexagonal plane shape, and such protrude portions aretwo-dimensionally arranged in the form of a honeycomb and recessedportions are formed as surrounding individual protruded portions. Thisenables one to extract light emitted from the active layer in anefficient manner in all directions of 360 degrees. Alternatively, therecessed portion may have a hexagonal plane shape, with which therecessed portions are two-dimensionally arranged in a honeycomb form soas to surround individual recessed portions with the protruded portions.Where the recessed portion of the substrate is in a striped form, thisrecessed portion extends, for example, along the <1-100> direction ofthe first nitride-based III-V group compound semiconductor layer. Thesection of the recessed portion may take various forms such as arectangle, an inverted trapezoid and the like, and side walls mayinclude a flat face, but also a curved face having a gentle slope, andcorners may be rounded. From the standpoint of improving a lightextraction efficiency, it is preferred that the section of the recessedportion is in the form of an inverted trapezoid. In this case, it ispreferred from the standpoint of minimizing the dislocation density inthe second nitride-based III-V group compound semiconductor layer thatwhen a depth of the recessed portion is taken as d, a width of thebottom surface of the recessed portion is taken as W_(g) and an angleestablished between the inclined face of the first nitride-based III-Vgroup compound semiconductor layer in a state of a triangle in sectionand the one main surface of the substrate is taken as α, d, W_(g) and αare so determined as to establish the relation of 2d≧W_(g) tan α. Sinceα is ordinarily constant, d and W_(g) are so determined as to establishthe inequality. If d is too large, starting gases are not satisfactorilysupplied inside the recessed portion, thereby impeding the formation ofthe first nitride-based III-V group compound semiconductor layer fromthe bottom of the recessed portion. In contrast, if d is too small, thefirst nitride-based III-V group compound semiconductor layer is grownnot only at the recessed portion of the substrate, but also at portionsat opposite sides (usually, protruded portions) thereof. From thestandpoint of preventing such formation, it is usual to select it withina range of 0.5 μm<d<5 μm, preferably within a range of 1.0±0.2 μm. W_(g)is generally within a range of 0.5 to 5 μm, preferably 2±0.5 μm.Although the width W_(t) at the upper surface of the protruded portionis basically selected arbitrarily, the protruded portion is a regionwhich is used for lateral growth of the second nitride-based III-V groupcompound semiconductor layer, so that a larger width leads to a largerarea of a portion with a reduced dislocation density. W_(t) is generallywithin a range of 1 to 1000 μm, preferably 4±2 μm.

From the view of growing the first nitride-based III-V group compoundsemiconductor layer at the recessed portions of the substrate, anamorphous layer may be formed over the substrate at opposite sides ofthe recessed portion. The amorphous layer is to be a growth mask. Thisis because nucleic formation is unlikely to occur on an amorphous layerupon growth. The amorphous layer may be formed, for example, bysubjecting a surface layer of a single crystal substrate to ionimplantation for amorphousization or by forming over the substrate byany of a variety of film formation methods. The amorphous layer is madeof an amorphous Si (a-Si) film including, for example, a SiO₂ film, aSiN film (including not only a Si₃N₄ film, but also those films havingdifferent compositions formed by a plasma CVD method), and a SiON film(including a case where a ratio between O and N is changed and arefractive index and a side face shape are in conformity with a desireddesign) and is generally an insulating film. Moreover, the substrate maybe formed at opposite sides of individual recessed portions successivelywith a first amorphous layer, a second amorphous layer and a thirdamorphous layer for use as a growth mask upon growth of the firstnitride-based III-V group compound semiconductor layer. In this case,the second amorphous layer should be one which can be selectivelyetched, for example, relative to the first and third amorphous layers.

After lateral growth of the second nitride-based III-V group compoundsemiconductor layer, the following procedure may be possible, in whichportions other than those above individual recessed portions of thesecond nitride-based III-V group compound semiconductor layer areremoved, followed by further lateral growth of the third nitride-basedIII-V group compound semiconductor layer on the second nitride-basedIII-V group compound semiconductor layer left over the recessed portionsand successive growth of an active layer and a fourth nitride-basedIII-V group compound semiconductor layer on the third nitride-basedIII-V group compound semiconductor layer. Alternatively, after thelateral growth of the second nitride-based III-V group compoundsemiconductor layer, another procedure may be possible, in whichportions other than those located above individual recessed portions ofthe second nitride-based III-V group compound semiconductor layer may beremoved, followed by lateral growth of a fifth nitride-based III-V groupcompound semiconductor layer on the second nitride-based III-V groupcompound semiconductor layer left over the recessed portions andsuccessive growth of the third nitride-based III-V group compoundsemiconductor layer, the active layer and the fourth nitride-based III-Vgroup compound semiconductor layer on the fifth nitride-based III-Vgroup compound semiconductor layer.

The third nitride-based III-V group compound semiconductor layer isformed with an electrode of a first conduction type in electricconnection or contact therewith. Likewise, an electrode of a secondconduction type is formed at the fourth nitride-based III-V groupcompound semiconductor layer in a state electrically connected to thefourth layer.

The substrate may be made of a variety of materials. For a substratemade of a material of the type that is different from a nitride-basedIII-V group compound semiconductor layer, specific mention is made, forexample, of substrates made of sapphire (of c, a, r faces and also of anoff face thereof), SiC (including 6H, 4H and 3C). Si, ZnC, ZnO, LiMgO,GaAs, MgAl₂O₄ and the like. Preferably, there are used hexagonal orcubic substrates made of these materials, more preferably hexagonalsubstrates. Alternatively, substrates made of nitride-based III-V groupcompound semiconductors such as GaN, InAlGaN, AlN and the like may alsobe used. Still alternatively, those substrates obtained by growing anitride-based III-V group compound semiconductor layer on a substratemade of a material different in type from the nitride-based III-V groupcompound semiconductor and forming recessed portions in thisnitride-based III-V group compound semiconductor layer. In addition,there may be used another type of substrate wherein a substrate made ofa material different from a nitride-based III-V group compoundsemiconductor is formed thereon with a layer made of a materialdifferent in type from a nitride-based III-V group compoundsemiconductor as a stacked polycrystal or amorphous layer of at leastone type of material, followed by patterning the layer partly to thedepth of the substrate thereby forming a patterned indented surface.

It will be noted that the substrate may be removed, if necessary.

The nitride-based III-V group compound semiconductor layer used as thefirst to fifth nitride-based III-V group compound semiconductor layersand the active layer is most commonly made of a semiconductor of theformula Al_(x)B_(y)Ga_(1-x-y-z)In_(z)As_(u)N_(1-u-v)P_(v) wherein 0≦x≦1,0≦y≦1, 0≦z≦1, 0≦u≦1, and 0≦v≦1 provided that 0≦x+y+z<1 and 0≦u+v<1.Preferably, mention is made of Al_(x)B_(y)Ga_(1-x-y-z)In_(z)N wherein0≦x≦1, 0≦y≦1, 0≦z≦1, and 0≦x+y+z<1. More preferably, the semiconductorlayer is made of Al_(x)Ga1-x-zInzN wherein 0≦x≦1 and 0≦z≦1. Specificexamples include GaN, InN, AlN, AlGaN, InGaN, AlGaInN and the like. Thefirst nitride-based III-V group compound semiconductor layer to beburied in the recessed portions of a substrate is preferably made ofGaN, In_(x)Ga_(1-x)N wherein 0<x<0.5, Al_(x)Ga_(1-x)N wherein 0<x<0.5,Al_(x)In_(y)Ga_(1-x-y)N wherein 0<x<0.5 and 0<y<0.2. The firstconduction type may be either an n-type or a p-type and,correspondingly, the second conduction type may be either a p-type or ann-type.

For the growth of the nitride-based III-V group compound semiconductorlayer constituting the first to fifth nitride-based III-V group compoundsemiconductor layers and the active layer, there may be used, forexample, a metallo-organic chemical vapor deposition (MOCVD), a hydrideor halide vapor phase epitaxy (HVPE), a molecular beam epitaxy (MBE) andother many epitaxies.

According to a second embodiment of the present invention, there isprovided a light-emitting diode, which including: a substrate having atleast one recessed portion on one main surface thereof; a sixthnitride-based III-V group compound semiconductor layer grown on thesubstrate without forming a space in the recessed portion; and a thirdnitride-based III-V group compound semiconductor layer of a firstconduction type, an active layer and a fourth nitride-based III-V groupcompound semiconductor layer of a second conduction type formed over thesixth nitride-based III-V group compound semiconductor layer. In thelight-emitting diode, a dislocation occurring, in the sixthnitride-based III-V group compound semiconductor layer, from aninterface with a bottom surface of the recessed portion in a directionvertical to the one main surface may arrive at an inclined face or itsvicinity of a triangle having the bottom surface of the recessed portionas a base thereof and bend in a direction parallel to the one mainsurface.

According to a third embodiment of the present invention, there isprovided a light-emitting diode, which including: a substrate having atleast one recessed portion on one main surface thereof; a sixthnitride-based III-V group compound semiconductor layer grown on thesubstrate without forming a space in the recessed portion; and a thirdnitride-based III-V group compound semiconductor layer of a firstconduction type, an active layer and a fourth nitride-based III-V groupcompound semiconductor layer of a second conduction type formed over thesixth nitride-based III-V group compound semiconductor layer. In thelight-emitting diode, the substrate may have a first pit having a firstwidth at a bottom of the recessed portion and a second pit having asecond width larger than the first width at opposite sides of therecessed portion.

In the second and third embodiments and also in fifth, sixth and eighthto seventeenth embodiments, appearing hereinafter, of the presentinvention, the sixth nitride-based III-V group compound semiconductorlayer corresponds to the first nitride-based III-V group compoundsemiconductor layer and the second nitride-based III-V group compoundsemiconductor layer in the first embodiment, respectively.

It should be noted that all the illustrations related to the firstembodiment may be likewise true of the second and third embodiments ofthe present invention and the fourth to eighteenth embodiments appearinghereinafter unless otherwise stated or unless otherwise needed inindividual embodiments.

According to a fourth embodiment of the present invention, there isprovided a method for making an integrated light-emitting diode having aplurality of light-emitting diodes integrated therein, which includingthe steps of: growing a first nitride-based III-V group compoundsemiconductor layer in at least one recessed portion formed at one mainsurface of a substrate through a state of making a triangle in sectionusing a bottom surface of the recessed portion as a base thereby buryingthe recessed portion therewith; laterally growing a second nitride-basedIII-V group compound semiconductor layer from the first nitride-basedIII-V group compound semiconductor layer over the substrate; andsuccessively growing, over the second nitride-based III-V group compoundsemiconductor layer, a third nitride-based III-V group compoundsemiconductor layer of a first conduction type, an active layer and afourth nitride-based III-V group compound semiconductor layer.

According to a fifth embodiment of the present invention, there isprovided an integrated light-emitting diode having a plurality oflight-emitting diodes integrated therein, at least one light emittingdiode thereof including: a substrate having at least one recessedportion on one main surface thereof; a sixth nitride-based III-V groupcompound semiconductor layer grown on the substrate without forming aspace in the recessed portion; and a third nitride-based III-V groupcompound semiconductor layer of a first conduction type, an active layerand a fourth nitride-based III-V group compound semiconductor layer of asecond conduction type formed over the sixth nitride-based III-V groupcompound semiconductor layer. In the light-emitting diode, a dislocationoccurring, in the sixth nitride-based III-V group compound semiconductorlayer, from an interface with a bottom surface of the recessed portionin a direction vertical to the one main surface may arrive at aninclined face or its vicinity of a triangle having the bottom surface ofthe recessed portion as a base thereof and bend in a direction parallelto the one main surface.

According to a sixth embodiment of the present invention, there isprovided an integrated light-emitting diode having a plurality oflight-emitting diodes integrated therein, at least one light-emittingdiode including: a substrate having at least one recessed portion on onemain surface thereof; a sixth nitride-based III-V group compoundsemiconductor layer grown on the substrate without forming a space inthe recessed portion; and a third nitride-based III-V group compoundsemiconductor layer of a first conduction type, an active layer and afourth nitride-based III-V group compound semiconductor layer of asecond conduction type formed over the sixth nitride-based III-V groupcompound semiconductor layer. In the light-emitting diode, the substratemay have a first pit having a first width at a bottom of the recessedportion and a second pit having a second width larger than the firstwidth at opposite sides of the recessed portion.

In the fourth to sixth embodiments of the present invention, theintegrated light-emitting diodes can be used in a variety of uses in thefield. Typical utility is directed to light-emitting diode backlightssuch as a liquid crystal display, a light-emitting diode lightingapparatus, a light-emitting diode display and the like. The integratedlight-emitting diode may be arbitrary with respect to the manner andform of arrangement of light-emitting diodes. For instance,light-emitting diodes may be arranged in two-dimensional arrays, or maybe such that striped light-emitting diodes are arranged in one line orplural lines. The form of the integrated light-emitting diode includes aform wherein a wafer having a stacked structure of semiconductor layersis block-processed according to a so-called semiconductor processingtechnique to provide circuit patterns and individual light-emittingdiodes integrated and arranged microfinely in plurality or a form whereindividual light-emitting diodes that have been microchipped beforehandare microfinely, plurally arranged over a circuit pattern or patterns.In addition, these light-emitting diodes may be driven independently orall in together. Alternatively, a group of light-emitting diodes withinan optionally set region may be driven independently in block (i.e. areadrive).

According to a seventh embodiment of the present invention, there isprovided a method for growing a nitride-based III-V group compoundsemiconductor layer, which including the steps of: providing a substratehaving at least one recessed portion on one main surface thereof andgrowing a first nitride-based III-V group compound semiconductor layerthrough a state of making a triangle in section having a bottom surfaceof the recessed portion as a base thereof thereby burying the recessedportion; and laterally growing a second nitride-based III-V groupcompound semiconductor layer from the first nitride-based compoundsemiconductor layer over the substrate.

This growth method of the nitride-based III-V group compoundsemiconductor may be applied to not only to the manufacture of alight-emitting diode and an integrated light-emitting diode, and also tothe manufacture of various types of semiconductor devices.

According to an eighth embodiment of the present invention, there isprovided a substrate for growth of a nitride-based III-V group compoundsemiconductor, which including: a substrate having at least one recessedportion on one main surface thereof; and a sixth nitride-based III-Vgroup compound semiconductor layer grown on the substrate withoutforming a space in the recessed portion. In the substrate, a dislocationoccurring from an interface with a bottom surface of the recessedportion in a direction vertical to the one main surface in the sixthnitride-based III-V group compound semiconductor layer may arrive at aninclined face or its vicinity of a triangle having the bottom surface ofthe recessed portion as a base thereof and bend in a direction parallelto the one main surface.

According to a ninth embodiment of the present invention, there isprovided a substrate for growth of a nitride-based III-V group compoundsemiconductor, which including: a substrate having at least one recessedportion on one main surface thereof; and a sixth nitride-based III-Vgroup compound semiconductor layer grown on the substrate withoutforming a space in the recessed portion. The substrate may have a firstpit having a first width at a bottom of the recessed portion and asecond pit having a second width larger than the first width at oppositesides of the recessed portion.

According to a tenth embodiment of the present invention, there isprovided a light source cell unit which includes a printed circuit boardand a plurality of cells formed on the printed circuit board, each cellcontaining at least one red light-emitting diode, at least one greenlight-emitting diode and at least one blue light-emitting diode. In thelight source cell unit, at least one of the red light-emitting diode,the green light-emitting diode and the blue light-emitting diode mayinclude: a substrate having at least one recessed portion on one mainsurface thereof; a sixth nitride-based III-V group compoundsemiconductor layer grown on the substrate without forming a space inthe recessed portion; and a third nitride-based III-V group compoundsemiconductor layer of a first conduction type, an active layer and afourth nitride-based III-V group compound semiconductor layer of asecond conduction type formed over the sixth nitride-based III-V groupcompound semiconductor layer. And a dislocation occurring from aninterface with a bottom surface of the recessed portion in a directionvertical to the one main surface in the sixth nitride-based III-V groupcompound semiconductor layer may arrive at an inclined face or itsvicinity of a triangle having the bottom surface of the recessed portionas a base thereof and bend in a direction parallel to the one mainsurface.

According to an eleventh embodiment of the present invention, there isprovided a light-emitting diode backlight which includes plural redlight-emitting diode, plural green light-emitting diode and plural bluelight-emitting diode arranged in pattern. In the light-emitting diode,at least one of the red light-emitting diode, the green light-emittingdiode and the blue light-emitting diode may include: a substrate havingat least one recessed portion on one main surface thereof; a sixthnitride-based III-V group compound semiconductor layer grown on thesubstrate without forming a space in the recessed portion; and a thirdnitride-based III-V group compound semiconductor layer of a firstconduction type, an active layer and a fourth nitride-based III-V groupcompound semiconductor layer of a second conduction type formed over thesixth nitride-based III-V group compound semiconductor layer. And adislocation occurring, in the sixth nitride-based III-V group compoundsemiconductor layer, from an interface with a bottom surface of therecessed portion in a direction vertical to the one main surface mayarrive at an inclined face or its vicinity of a triangle having thebottom surface of the recessed portion as a base thereof and bend in adirection parallel to the one main surface.

According to a twelfth embodiment of the present invention, there isprovided a light-emitting diode backlight which includes a redlight-emitting diode, a green light-emitting diode and a bluelight-emitting diode arranged in pattern, each being plural in number,wherein at least one of the red light-emitting diode, the greenlight-emitting diode and the blue light-emitting diode includes: asubstrate having at least one recessed portion on one main surfacethereof; a sixth nitride-based III-V group compound semiconductor layergrown on the substrate without forming a space in the recessed portion;and a third nitride-based III-V group compound semiconductor layer of afirst conduction type, an active layer and a fourth nitride-based III-Vgroup compound semiconductor layer of a second conduction type formedover the sixth nitride-based III-V group compound semiconductor layer,wherein the substrate has a first pit having a first width at a bottomof the recessed portion and a second pit having a second width largerthan the first width at opposite sides of the recessed portion.

According to a thirteenth embodiment of the present invention, there isprovided a light-emitting diode lighting apparatus which includes a redlight-emitting diode, a green light-emitting diode and a bluelight-emitting diode arranged in pattern, each being plural in number,wherein at least one of the red light-emitting diode, the greenlight-emitting diode and the blue light-emitting diode includes: asubstrate having at least one recessed portion on one main surfacethereof; a sixth nitride-based III-V group compound semiconductor layergrown on the substrate without forming a space in the recessed portion;and a third nitride-based III-V group compound semiconductor layer of afirst conduction type, an active layer and a fourth nitride-based III-Vgroup compound semiconductor layer of a second conduction type formedover the sixth nitride-based III-V group compound semiconductor layer,wherein a dislocation occurring, in the sixth nitride-based III-V groupcompound semiconductor layer, from an interface with a bottom surface ofthe recessed portion in a direction vertical to the one main surfacearrives at an inclined face or its vicinity of a triangle having thebottom surface of the recessed portion as a base thereof and bends in adirection parallel to the one main surface.

According to a fourteenth embodiment of the present invention, there isprovided a light-emitting diode lighting apparatus which includes a redlight-emitting diode, a green light-emitting diode and a bluelight-emitting diode arranged in pattern, each being plural in number,wherein at least one of the red light-emitting diode, the greenlight-emitting diode and the blue light-emitting diode includes: asubstrate having at least one recessed portion on one main surfacethereof; a sixth nitride-based III-V group compound semiconductor layergrown on the substrate without forming a space in the recessed portion;and a third nitride-based III-V group compound semiconductor layer of afirst conduction type, an active layer and a fourth nitride-based III-Vgroup compound semiconductor layer of a second conduction type formedover the sixth nitride-based III-V group compound semiconductor layer,wherein the substrate has a first pit having a first width at a bottomof the recessed portion and a second pit having a second width largerthan the first width at opposite sides of the recessed portion.

According to a fifteenth embodiment of the present invention, there isprovided a light-emitting diode display which includes a redlight-emitting diode, a green light-emitting diode and a bluelight-emitting diode arranged in pattern, each being plural in number,wherein at least one of the red light-emitting diode, the greenlight-emitting diode and the blue light-emitting diode includes: asubstrate having at least one recessed portion on one main surfacethereof; a sixth nitride-based III-V group compound semiconductor layergrown on the substrate without forming a space in the recessed portion;and a third nitride-based III-V group compound semiconductor layer of afirst conduction type, an active layer and a fourth nitride-based III-Vgroup compound semiconductor layer of a second conduction type formedover the sixth nitride-based III-V group compound semiconductor layer,wherein a dislocation occurring, in the sixth nitride-based III-V groupcompound semiconductor layer, from an interface with a bottom surface ofthe recessed portion in a direction vertical to the one main surfacearrives at an inclined face or its vicinity of a triangle having thebottom surface of the recessed portion as a base thereof and bends in adirection parallel to the one main surface.

According to a sixteenth embodiment of the present invention, there isprovided a light-emitting diode display which includes a redlight-emitting diode, a green light-emitting diode and a bluelight-emitting diode arranged in pattern, each being plural in number,wherein at least one of the red light-emitting diode, the greenlight-emitting diode and the blue light-emitting diode includes: asubstrate having at least one recessed portion on one main surfacethereof; a sixth nitride-based III-V group compound semiconductor layergrown on the substrate without forming a space in the recessed portion;and a third nitride-based III-V group compound semiconductor layer of afirst conduction type, an active layer and a fourth nitride-based III-Vgroup compound semiconductor layer of a second conduction type formedover the sixth nitride-based III-V group compound semiconductor layer,wherein the substrate has a first pit having a first width at a bottomof the recessed portion and a second pit having a second width largerthan the first width at opposite sides of the recessed portion.

In the tenth to sixteenth embodiments of the present invention, the redlight-emitting diode may be one that makes use, for example, of anAlGaInP semiconductor.

According to a seventeenth embodiment of the present invention, there isprovided an electronic device including at least one light-emittingdiode, the at least one light-emitting diode including: a substratehaving at least one recessed portion on one main surface thereof; asixth nitride-based III-V group compound semiconductor layer grown onthe substrate without forming a space in the recessed portion; and athird nitride-based III-V group compound semiconductor layer of a firstconduction type, an active layer and a fourth nitride-based III-V groupcompound semiconductor layer of a second conduction type formed over thesixth nitride-based III-V group compound semiconductor layer, wherein adislocation occurring, in the sixth nitride-based III-V group compoundsemiconductor layer, from an interface with a bottom surface of therecessed portion in a direction vertical to the one main surface arrivesat an inclined face or its vicinity of a triangle having the bottomsurface of the recessed portion as a base thereof and bends in adirection parallel to the one main surface.

According to an eighteenth embodiment of the present invention, there isprovided an electronic device which includes at least one light-emittingdiode, the at least one light-emitting diode including: a substratehaving at least one recessed portion on one main surface thereof; asixth nitride-based III-V group compound semiconductor layer grown onthe substrate without forming a space in the recessed portion; and

a third nitride-based III-V group compound semiconductor layer of afirst conduction type, an active layer and a fourth nitride-based III-Vgroup compound semiconductor layer of a second conduction type formedover the sixth nitride-based III-V group compound semiconductor layer,wherein the substrate has a first pit having a first width at a bottomof the recessed portion and a second pit having a second width largerthan the first width at opposite sides of the recessed portion.

In the seventeenth and eighteenth embodiments of the present invention,the electronic device include, aside from a light-emitting diodebacklight (e.g. a backlight for a liquid crystal display or the like), alight-emitting diode lighting apparatus, a light-emitting diode displayand the like, a projector using a light-emitting diode as a lightsource, a rear projection television, a grating light valve (GLV) andthe like. In general, the electronic device may fundamentally be of anytype provided that it has at least one light-emitting diode for thepurpose of display, lighting, optical communication, opticaltransmission and the like, and may include both portable and desktopones. Specific examples other than those indicated above include a cellphone, a mobile device, a robot, a personal computer, a on-vehicledevice, a variety of domestic electric products, a light-emitting diodeoptical communication device, a light-emitting diode opticaltransmission device and the like. Electronic devices further includecombinations of two or more types of light-emitting diodes capable ofemitting light of different wavelengths in wavelength ranges including afar-infrared wavelength range, an infrared wavelength range, a redwavelength range, a yellow wavelength range, a green wavelength range, ablue wavelength range, a purple wavelength range, a ultravioletwavelength range and the like. Especially, with a light-emittinglighting device, two or more light-emitting diodes, which are capable ofemitting visible light of different wavelength ranges selected among ared wavelength range, a yellow wavelength range, a green wavelengthrange, a blue wavelength range and a purple wavelength range. Tow ormore types of light emitted from these light-emitting diodes are mingledto obtain natural light or white light. Moreover, using, as a lightsource, a light-emitting diode capable of emitting light within at leastone wavelength range of the blue light wavelength range, purplewavelength range and ultraviolet wavelength range, light emitted formthis light-emitting diode is irradiated against a fluorescent body andthe light obtained by excitation of the body is mingled therewith toobtain natural light or white light.

According to a nineteenth embodiment of the present invention, there isprovided a method for making an electronic device, which including thesteps of: providing a substrate having at least one recessed portion onone main surface and growing a first layer at the recessed portionthrough a state of making a triangle in section having a bottom surfaceof the recessed portion as a base and burying the recessed portion; andlaterally growing a second layer from the first nitride-based compoundsemiconductor layer over the substrate.

According to a twentieth embodiment of the present invention, there isprovided an electronic device, which including: a substrate having atleast one recessed portion on one main surface; and a third layer formedon the substrate and grown without forming a space in the recessedportion, wherein a dislocation occurring, in the third layer, from aninterface with a bottom surface of the recessed portion in a directionvertical to the one main surface arrives at an inclined face or itsvicinity of a triangle having the bottom surface of the recessed portionas a base and bends in a direction parallel to the one main surface.

In the nineteenth and twentieth embodiments of the present invention,the first to third layers may be made, aside from a nitride-based III-Vgroup compound semiconductor, of other types of semiconductors having awurtzit structure or more generally, a hexagonal crystal structure, e.g.ZnO, α-ZnS, α-CdS, α-CdSe and the like, and a variety of semiconductorshaving other crystal structures. Semiconductor devices using thesesemiconductors include light-emitting devices such as ordinarylight-emitting diodes, inter-subband transition (quantum cascade)light-emitting diodes, ordinary semiconductor lasers, inter-subbandtransition (quantum cascade) semiconductor lasers and the like, alsolight-receiving devices such as photodiodes, sensors, solar cells, andelectron transit devices typical of which are transistors including anfield effect transistor (FET) such as a high electron mobilitytransistor and a bipolar transistor such as a heterojunction bipolartransistor (HBT). These devices may be mounted on the same substrate orchip singly or plurally. These devices may be so arranged to be drivenindependently, if necessary. The optical electronic IC (OEIC) can beconstructed by integrating light-emitting devices and electron transitdevices on the same substrate. An optical wiring can be formed accordingto need. In addition, when at least one light-emitting device(light-emitting diode or semiconductor laser) is used to permit light toflush, lighting communication or optical communication can be performed.In this case, lighting communication or optical communication may becarried out using a plurality of light beams of different wavelengthranges.

The electronic devices include, aside from such semiconductor devices,(e.g. light-emitting devices, light-receiving devices, electron transitdevices and the like), piezoelectric devices, pyroelectric devices,optical devices (such as a second-order harmonic generator using anonlinear optical crystal, a dielectric device including aferrodielectric device), and a superconduction device and the like. Inthis connection, the materials for the first to third layers may includea variety of semiconductors as indicated above and particularly with thepiezoelectric device, pyroelectric device, optical device, dielectricdevice, and superconducting device, many materials such as oxides havinga hexagonal crystal structure can be used.

When using those electronic devices including a light-emitting diode ora semiconductor laser, there can be provided a light-emitting diodebacklight, a light-emitting diode lighting device, a light-emittingdiode display, a projector or a rear projection television using alight-emitting diode or a semiconductor laser as a light source, andelectronics such as a grating light valve.

With respect to the nineteenth and twentieth embodiments of the presentinvention, such applications as in the first to eighteenth embodimentsare likewise possible.

According to the embodiments of the present invention as statedhereinabove, a first nitride-based III-V group compound semiconductorlayer starts to grow from a bottom of a recessed portion of a substrate.During the course of the growth, the first nitride-based III-V groupcompound semiconductor layer is being formed through a state of making atriangle in section having the bottom as a base thereof thereby buryingthe recessed portion with the layer without a space in the recessedportion. Thereafter, a second nitride-based III-V group compoundsemiconductor layer is laterally grown from the thus grown firstnitride-based III-V group compound semiconductor layer. At this stage, adislocation occurs, in the first nitride-based III-V group compoundsemiconductor layer, from an interface with the bottom of the recessedportion of the substrate in a direction vertical to one main surface ofthe substrate. This dislocation arrives at an inclined face or itsvicinity of the first nitride-based III-V group compound semiconductorlayer, under which as the second nitride-based III-V group compoundsemiconductor layer grows, the dislocation bends therefrom in adirection parallel to the one main surface of the substrate. At the timewhen the second nitride-based III-V group compound semiconductor layeris grown to a satisfactory thickness, a portion above the dislocationparallel to the one main surface of the substrate becomes a region wherea dislocation density is very small. According to this method, the firstto fourth nitride-based III-V group compound semiconductor layers can begrown by one epitaxy.

More generally speaking, similar results may be likewise achieved whentaking the first nitride-based III-V group compound semiconductor layermerely as a first layer and the second nitride-based III-V groupcompound semiconductor layer merely as a second layer.

According to the embodiments of the present invention, no space or gapis formed between the first nitride-based III-V group compoundsemiconductor layer and second nitride-based III-V group compoundsemiconductor layer and the substrate, a light extraction efficiency canbe remarkably improved. Since crystallinity of the second nitride-basedIII-V group compound semiconductor layer becomes good, thecrystallinities of the third nitride-based III-V group compoundsemiconductor layer, active layer and fourth nitride-based III-V groupcompound semiconductor layer grown on the second layer can be remarkablyimproved. Eventually, a light-emitting diode having a very high lightemission efficiency. In addition, since the light-emitting diode can bemade by one epitaxy, the manufacturing costs are low. Thus, there can berealized the manufacture of a high-performance light source cell unit,light-emitting diode backlight, light-emitting diode lighting device andlight-emitting diode display, and various types of electronics using thelight-emitting diode of this high light emission efficiency.

More generally, similar results may be obtained when the firstnitride-based III-V group compound semiconductor layer is taken as afirst layer and the second nitride-based III-V group compoundsemiconductor layer taken as a second layer.

The above and other features and advantages of the present inventionwill become apparent from the following description when taken inconjunction with the accompanying drawings which illustrate preferredembodiments of the present invention by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F are, respectively, a sectional view illustrating a methodfor making a GaN light-emitting diode according to a first embodiment ofthe present invention;

FIG. 2 is a plan view showing an instance of a planar shape of recessedportions and protruded portions formed on a sapphire substrate in themethod for making a GaN light-emitting diode according to the firstembodiment of the present invention;

FIG. 3 is a schematic view showing how to extract light from a GaNlight-emitting diode obtained by the first embodiment of the presentinvention;

FIG. 4 is a schematic view showing a sapphire substrate used in themethod for making a GaN light-emitting diode according to the firstembodiment of the present invention;

FIG. 5 is a schematic view illustrating how a GaN layer is grown on thesapphire substrate in the method for making a GaN light-emitting diodeaccording to the first embodiment of the present invention;

FIG. 6 is a schematic view showing a distribution of crystal defects inthe GaN grown on the sapphire substrate in the method for making a GaNlight-emitting diode according to the first embodiment of the presentinvention;

FIG. 7 is a photograph showing a planar cathode luminescence image ofthe GaN layer grown on the sapphire substrate in the method for making aGaN light-emitting diode according to the first embodiment of thepresent invention;

FIGS. 8A and 8B are, respectively, a schematic view illustrating thebehavior of dislocations obtained through TEM observation of the GaNlayer grown on the sapphire substrate in the method for making a GaNlight-emitting diode according to the first embodiment of the presentinvention;

FIG. 9 is a schematic view illustrating the results of estimation of adislocation density in the GaN layer grown on the sapphire substrate inthe method for making a GaN light-emitting diode according to the firstembodiment of the present invention;

FIGS. 10A and 10B are, respectively, a micrograph showing the results ofsectional TEM observation of an interface with the GaN layer grown onthe sapphire substrate in the method for making a GaN light-emittingdiode according to the first embodiment of the present invention;

FIG. 11 is a schematic view illustrating formation of a pit upon growthof the GaN layer on the sapphire substrate in the method for making aGaN light-emitting diode according to the first embodiment of thepresent invention;

FIGS. 12A to 12C are, respectively, a micrograph showing the results ofsectional TEM observation of an interface with the GaN layer grown onthe sapphire substrate in the method for making a GaN light-emittingdiode according to the first embodiment of the present invention;

FIGS. 13A and 13B are a schematic view illustrating a distribution inthickness of the GaN layer shown in FIGS. 12B and 12C, respectively;

FIG. 14 is a schematic view showing the results of lay tracingsimulation of the GaN light-emitting diode made according to the firstembodiment of the present invention;

FIG. 15 is a schematic view illustrating optimization conditions forimproving a light extraction efficiency of the GaN light-emitting diodemade according to the first embodiment of the present invention;

FIG. 16 is a graph showing the results of simulation of an area ratio ofinclined surface of the sapphire substrate employed in the GaNlight-emitting diode according to the first embodiment of the presentinvention;

FIG. 17 is a graph showing the results of simulation of an area ratio ofinclined surface of the sapphire substrate employed in the method formaking a GaN light-emitting diode according to the first embodiment ofthe present invention;

FIG. 18 is a graph showing the results of simulation of an area ratio ofan inclined surface of the sapphire substrate employed in the method formaking a GaN light-emitting diode according to the first embodiment ofthe present invention;

FIG. 19 is a schematic view illustrating surface flatness of an activelayer of the GaN light-emitting diode made according to the firstembodiment of the present invention;

FIG. 20 is a schematic view illustrating surface flatness of an activelayer of the GaN light-emitting diode made according to the firstembodiment of the present invention;

FIGS. 21A to 21E are, respectively, a sectional view illustrating amethod for making a GaN light-emitting diode according to a secondembodiment of the present invention;

FIGS. 22A to 22G are, respectively, a sectional view illustrating amethod for making a GaN light-emitting diode according to a thirdembodiment of the present invention;

FIGS. 23A to 23F are, respectively, a sectional view illustrating amethod for making a GaN light-emitting diode according to a fourthembodiment of the present invention;

FIGS. 24A to 24G are, respectively, a sectional view illustrating amethod for making a GaN light-emitting diode according to a fifthembodiment of the present invention;

FIGS. 25A to 25G are, respectively, a sectional view illustrating amethod for making a GaN light-emitting diode according to a sixthembodiment of the present invention;

FIGS. 26A and 26B are, respectively, a sectional view illustrating amethod for making a GaN light-emitting diode according to a seventhembodiment of the present invention;

FIGS. 27A to 27J are, respectively, a sectional view illustrating amethod for making a GaN light-emitting diode according to an eighthembodiment of the present invention;

FIGS. 28A to 28C are, respectively, a sectional view illustrating amethod for making a GaN light-emitting diode backlight according to aninth embodiment of the present invention;

FIGS. 29A and 29B are, respectively, a perspective view illustrating themethod according to the ninth embodiment of the present invention;

FIG. 30 is a perspective view illustrating a method for making alight-emitting diode backlight according to a tenth embodiment of thepresent invention;

FIG. 31 is a perspective view illustrating an integrated light-emittingdiode made according to an eleventh embodiment of the present invention;

FIG. 32 is a sectional view showing the integrated light-emitting diode,made according to the eleventh embodiment of the present invention,mounted on a submount;

FIGS. 33A and 33B are, respectively, a plan view showing a light sourcecell unit according to a twelfth embodiment of the present invention andan enlarged view of a cell of the light source cell unit;

FIGS. 34A and 34B are, respectively, a plan view showing a specificexample of the light source cell unit according to the twelfthembodiment of the present invention;

FIG. 35 is a plan view showing an example showing another cellarrangement of the light source cell unit according to the twelfthembodiment of the present invention;

FIGS. 36A to 36C are, respectively, a sectional view illustrating arelated method of growing a GaN semiconductor layer on an indentedsubstrate;

FIG. 37 is a sectional view illustrating a problem of the related methodshown in FIG. 36;

FIGS. 38A to 38D are, respectively, a sectional view illustrating arelated method of growing a GaN semiconductor layer on an indentedsubstrate; and

FIGS. 39A to 39F are, respectively, a sectional view illustratinganother related method of growing a GaN semiconductor substrate on anindented substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention are illustrated with reference tothe accompanying drawings. It will be noted that like reference numeralsindicate like parts or members throughout the drawings.

FIGS. 1A to 1F are views showing, in the order of steps, a method formaking a GaN light-emitting diode according to a first embodiment of thepresent invention.

In this first embodiment, as shown in FIG. 1A, a sapphire substrate 11having a patterned indentation on one main surface thereof is provided.Reference numeral 11 a indicates a recessed portion or recess andreference numeral 11 b indicates a protruded portion or protrusion. Inthis case, the recessed portion 11 a has an inverted trapezoid insection. For instance, the main surface of sapphire substrate 11 is ac-face and the recessed portion 11 a is in a striped form extending in a<1-100> direction of the sapphire substrate 11. Although the planarshapes of the recessed portion 11 a and the protruded portion 11 b maybe those ones set out hereinbefore, respectively, preferred instancesare shown in FIG. 2. In this instance, as shown in FIG. 2, each of theprotruded portions 11 b is hexagonal in plane and they aretwo-dimensionally arranged to be shaped as a honeycomb. The recessedportions 11 a are formed to surround individual protrusions 11 b. Thehexagonal protruded portion 11 b has a distance between facing sides ofthe hexagon, for example, at 3.8 to 4.2 μm, preferably at 4 μm. Thedistance between adjacent hexagonal protrusions 11 b is set, forexample, at 1.3 to 1.7 μm, preferably 1.5 μm although not limitative.Typically, the direction of the dotted line (i.e. a direction of a lineconnecting the centers of the most adjacent protruded portions 11 b) ismade parallel to an m axis of a GaN layer described hereinafter. Thesurface indentation of the sapphire substrate 11 may be carried outaccording to many methods including a reactive ion etching (RIE) method,a powder blasting technique, a sand blasting technique and the like. Thesizes of these recessed portion 11 a and protruded portion 11 b aredescribed hereinlater in detail.

Next, the sapphire substrate 11 is cleaned on the surfaces thereof suchas by thermal cleaning, followed by growing on the sapphire substrate11, for example, a GaN buffer layer (not shown) at a growth temperature,for example, of about 550° C. according to a known procedure.Subsequently, using, for example, a MOCVD method, GaN is epitaxiallygrown. At this stage, as shown in FIG. 1B, the growth starts initiallyfrom the bottom surface of the recessed portion 11 a, and a GaN layer 12is grown in such a way as to form an isosceles triangle in section thathas the bottom as a base and a facet inclined relative to the mainsurface of the sapphire substrate 11 as an inclined side. For instance,the GaN layer 12 extends in a <1-100> direction with the facet of theinclined side or surface thereof being a (1-101) face. This GaN layer 12may be either undoped or doped with an n-type or p-type impurity. Thegrowing conditions of the GaN layer 12 are described hereinafter.

Subsequently, the growth of the GaN layer 12 is so carried out whilekeeping the direction of the facet face of the inclined surface, therecessed portion 11 a is fully filled therein as shown in FIG. 1C. InFIG. 1C, dotted lines indicate a growth interface on the way of growth(hereinafter the same).

Next, when the growth is continued while setting the conditions wherelateral growth is predominant, the GaN layer 12 spreads over theprotruded portion 11 b while increasing the thickness thereof as shownin FIG. 1D. Finally, the GaN layers 12 growing from adjacent recessedportions 11 a mutually contact with each other over the protrudedportion 11 b.

Thereafter, as shown in FIG. 1E, the GaN layer 12 is laterally grown sothat the surface of the GaN layer 12 creates a flat surface in parallelto the main surface of the sapphire substrate 11. The thus grown GaNlayer 12 has a very low dislocation density above the recessed portion11 a.

Next, as shown in FIG. 1F, for example, an n-type GaInN layer 13, ann-type GaN layer 14, an n-type GaInN layer 15, an active layer 16, ap-type GaInN layer 17, a p-type AlInN layer 18, a p-type GaN layer 19and a p-type GaInN layer 20 are successively epitaxially formed on theGaN layer 12. The active layer 16 has, for example, a GaInN-basedmultilayered quantum well (MQW) structure (e.g. an alternating stack ofGaInN quantum well layers and GaN barrier layers). The In composition ofthe active layer 16 is selected depending the emission wavelength of alight-emitting diode and is, for example, at up to 11% for an emissionwavelength of 405 nm, at up to 18% for 450 nm, and at up to 24% for 520nm.

Thereafter, in order to activate the p-type impurities in the p-typeGaInN layer 17, p-type AlInN layer 18, p-type GaN layer 19 and p-typeGaInN layer 20, thermal treatment carried out in an atmosphere of amixed gas, for example, of N₂ and O₂ (with a composition, for example,of 99% of N₂ and 1% of O₂) at a temperature of 550 to 750° C. (e.g. 650°C.) or 580 to 620° C. (e.g. 600° C.). The activation is more likely tooccur when O₂ is mixed with N₂. The time for the thermal treatmentranges, for example, from five minutes to two hours, or 40 minutes totwo hours. In general, the time ranges from 10 to 60 minutes. The reasonwhy the thermal treatment temperature is suppressed to a level that isrelatively low is that the active layer 16 is prevented from degradationat the time of thermal treatment.

The starting material for the growth of the GaN semiconductor layerincludes, for example, as a Ga material, triethyl gallium ((C₂H₅)₃Ga,TEG) or trimethyl gallium ((CH₃)₃Ga, TMG), as an Al material, trimethylaluminium ((CH₃)₃Al, TMA), and as an In material, trimethyl indium((CH₃)₃In, TMI), and as a N material, ammonium (NH₃). Dopants include,for example, silane (SiH₄) as an n-type dopant, andbis(methylcyclopentadiene)magnesium ((CH₃C₅H₄)₂Mg),bis(ethylcyclopentadienyl)magnesium ((C₂H₅C₅H₄)₂Mg) orbis(cyclopentadienyl)magnesium ((C₅H₅)₂Mg) as a p-type dopant.

For the carrier gas atmosphere used to grow the GaN semiconductor layer,H₂ gas is used, for example.

Next, the sapphire substrate 11 on which the GaN semiconductor substratehas been formed in a manner as set out above is removed from the MOCVDapparatus.

Thereafter, a p-side electrode 21 is formed on the p-type GaInN layer20. The material for the p-side electrode 21 is made of an ohmic metalhaving a high reflectivity and is preferably Ag or Pd/Ag. It will benoted that the p-side electrode 21 may be formed after the epitaxialgrowth of the n-type GaInN layer 13, n-type GaN layer 14, n-type GaInNlayer 15, active layer 16, p-type GaInN layer 17, p-type AlInN layer 18,p-type GaN layer 19 and p-type GaInN layer 20 but prior to the thermaltreatment for activating the p-type impurities in the p-type GaInN layer17, p-type AlInN layer 18, p-type GaN layer 19 and p-type GaInN layer20.

Next, the n-type GaN layer 14, n-type GaInN layer 15, active layer 16,p-type GaInN layer 17, p-type AlInN layer 18, p-type GaN layer 19 andp-type GaInN layer 20 are patterned in a desired form, for example,according to a RIE method, a powder blasting method, a sand blastingmethod or the like to form a mesa portion 22.

Subsequently, an n-side electrode 23 is formed on the n-type GaInN layer13 at a portion adjacent to the mesa portion 22. The n-side electrode 23is one that has, for example, a Ti/Pt/Au structure.

Next, if necessary, the sapphire substrate 11 on which such alight-emitting diode structure as set forth hereinabove has been formedis cut off or lapped from the back side thereof to reduce its thickness,followed by scribing the sapphire substrate 11 and forming a bar.Thereafter, the bar is scribed for chipping.

In the resulting GaN light-emitting diode, as shown in FIG. 3, lightemission is performed by application a forward voltage between thep-side electrode 21 and the n-side electrode 23 to pass an electriccurrent therebetween, and light is taken through the sapphire substrate11 to outside. In FIG. 3, light is depicted as being taken out towardabove, so that the sapphire substrate 11 is laid uppermost. Properselection of an In composition of the active layer 16 ensures emissionof red to ultraviolet light, particularly, blue light, green light orred light. In this connection, a component of light generated from theactive layer 16, which is directed toward the sapphire substrate 11, isrefracted at an interface between the sapphire substrate 11 and the GaNlayer 12 in the recessed portion 11 a, after which it is discharged tooutside through the sapphire substrate 11. On the other hand a componentof the light generated from the active layer 16, which is directedtoward the p-side electrode 21, is reflected at the p-side electrode 21and is directed toward the sapphire substrate 11 and discharged tooutside through the sapphire substrate 11. It will be noted that thelight shown in FIG. 3 is one in the case where the refractive index ofthe GaN semiconductor layer constituting the light-emitting diode istaken as 2.438 that is a refractive index of GaN, the refractive indexof the sapphire substrate 11 is taken as 1.785, and the refractive indexof air is taken as 1.

In this first embodiment, in order to minimize a threading dislocationdensity of the GaN layer 12, a width W_(g) of the recessed portion 11 a,a depth d and an angle α made between the inclined face of the GaN layer12 in the state shown in FIG. 1B and the main surface of the sapphiresubstrate 11 are so determined to satisfy the following inequality (seeFIG. 4)

2d≧W_(g) tan α

For example, when W_(g)=2.1 μm and α=59 degrees, d≧1.75 μm. Likewise,d≧1.66 μm for the case where W_(g)=2 μm and α=59 degrees, d≧1.245 μm forthe case where W_(g)=1.5 μm and α=59 degrees, and d≧0.966 μm for thecase where W_(g)=1.2 μm and α=59 degrees. In either case, it ispreferred that d<5 μm.

At the stage of growing the GaN layer 12 in the steps shown in FIGS. 1Band 1C, a ratio between the starting materials V/III for the growth isset at a relatively high level, e.g. within a range of 13000±2000 andthe growing temperature is set at a relatively low level, e.g. within arange of 1050±50° C. This ensures the growth of the GaN layer 12 so asto fully bury the recessed portion 11 a therewith while permitting afacet inclined relative to the main surface of the substrate 11 toappear at the inclined surface as shown in FIGS. 1B and 1C. In thiscondition, little GaN layer 12 is grown over the protruded portions 11b. The growth of the GaN layer 12 is carried out at an atmosphericpressure, for example, of 1.0 to 2.0, preferably at about 1.6atmospheric pressures. This permits lateral growth to be suppressed andeasy selective growth of the GaN layer 12 to occur at the recessedportion 11 a. The growing rate generally ranges from 1.0 to 5.0 μm/hourand is preferably at about 3.0 μm/hour. The flow rates of the startinggases are, for example, at 20 SCCM for TMG and 20 SLM for NH₃. On theother hand, the growth (lateral growth) of the GaN layer 12 in the stepsshown in FIGS. 1D and 1E is carried out in such a way that a ratiobetween the starting materials V/III is set at a relatively low level,e.g. within a range of 5000±2000 and a growing temperature is set at arelatively high level, e.g. within a range of 1150±50° C. If the growingtemperature is higher than the above range, the resulting GaN layer 12is liable to be roughened on the surface thereof. On the other hand, ifthe temperature is lower, pits are apt to occur at a mutually associatedportion of the GaN layers 12. The flow rates of the starting gases are,for example, at 40 SCCM for TMG and 20 SLM for NH₃. In this way, the GaNlayer 12 is laterally grown as shown in FIGS. 1D and 1E to obtain a flatsurface. No space or void occurs between the GaN layer 12 and thesapphire substrate 11.

FIG. 5 schematically shows how starting gases run at the time of growthof the GaN layer 12 and diffuse over the sapphire substrate 11. The mostimportance in this growth is that no GaN layer 12 grows, at an initialstage of growth, at the protruded portion 11 b (terrace portion) of thesapphire substrate 11, but the GaN layer 12 starts to grow at therecessed portion 11 a. The reason for this is considered as follows. Ingeneral, when TMG is used as a starting material for Ga and NH₃ is usedas a starting material for N, the growth of GaN occurs by directreaction between NH₃ and Ga as expressed according to the followingreaction formulas

Ga(CH₃)₃ (gas)+ 3/2H₂ (gas)→Ga (gas)+3CH₄ (gas)

NH₃ (gas)→(1−α)NH₃ (gas)+α/2N₂ (gas)+3α/2H₂ (gas)

Ga (gas)+NH₃ (gas)=GaN (solid)+ 3/2H₂ (gas)

During the reactions, H₂ gas generates. This H₂ gas has a reverse actionto the crystal growth, i.e. an etching action. In the steps shown inFIGS. 1B and 1C, using conditions which are not performed for the growthof GaN on an employed flat substrate in related art, i.e. the conditions(of increasing a V/III value) where an etching action is enhanced andthe growth is unlikely to occur, growth at the protruded portion 11 b issuppressed. In this connection, this etching action is lessened insidethe recessed portion 11 a and thus, crystal growth takes place. In orderto improve the surface flatness of growing crystals, it used to grow thecrystals under conditions of increasing the degree of later growth (orat higher temperatures) in related art. In accordance with the firstembodiment, for the purposed of reducing threading dislocations innumber by bending them in a direction parallel to the main surface ofthe sapphire substrate 11 and also burying the recessed portion 11 awith the GaN layer 12 at an earlier stage, growth at temperatures lowerthan ones in related art as stated hereinabove (e.g. 1050±50° C.) iseffected.

FIG. 6 schematically shows the results of a crystal defect distributionof a GaN layer 12 determined by a transmission electron microscope(TEM). FIG. 7 shows a planar cathode luminescence (CL) image of thesurface of the GaN layer 12. As will be seen from FIG. 6, although adislocation density becomes high at a mutually associated portion of theGaN layers 12 growing from adjacent recessed portions 11 a, thedislocation density becomes low at the other portions including aportion above the recessed portion 11 a. For instance, with the casewhere the recessed portion has a depth d=1 μm and a width W_(g)=2 μm atthe bottom surface and the protruded portion 11 b has a width W_(t)=2 μmat the upper surface thereof, the dislocation density is 1×10⁷/cm² atthis portion of low dislocation density. Thus the dislocation density isreduced by one or two magnitudes of order over a case using a sapphiresubstrate 11 not subjected to surface indentation. It will be also seenthat no dislocation occurs in a direction vertical to the side walls ofthe recessed portion 11 a. The planar cathode luminescence image shownin FIG. 7 well coincides with the results of FIG. 6.

In FIG. 6, the average thickness of a region where the dislocationdensity of the GaN layer 12 in contact with the sapphire substrate 11 atthe recessed portion 11 a is high with poor crystallinity is about 1.5times an average thickness of a region, with poor crystallinity, of ahigh dislocation density of the GaN layer 12 in contact with thesapphire substrate 11 at the protruded portion 11 b. This resultreflects the lateral growth of the GaN layer 12 on the protruded portion11 b.

FIGS. 8A and 8B schematically show the behavior of dislocations in thecourse of growth of the GaN layer 12, which as been found in view of theresults of TEM analyses. FIG. 8A is a sectional view and FIG. 8B is aplan view corresponding to the section shown in FIG. 8A. Broadly,dislocations can be classified into two types.

The first type of dislocation (type-(a+c) dislocation) is illustratedbelow. In FIGS. 8A and 8B, dislocation (1) occurs from an interface withthe bottom of the recessed portion 11 a and bends in a horizontaldirection (i.e. in a direction parallel to the main surface of thesapphire substrate 11) at a facet (a) of the inclined side of anisosceles triangle using the bottom as a base. Dislocation (1)continually extends to the side wall of the recessed portion 11 a whereit disappears. Dislocation (2) occurs from an interface with the bottomof the recessed portion 11 a, bends in a horizontal direction at thefacet (a) and extends to the vicinity of a center of the protrudedportion 11 b. Then dislocation (2) bends toward above (in a directionvertical to the main surface of the sapphire substrate 11) at a facet(c) on association at the center of the protruded portion 11 b, andrises in a vertical direction at the associated portion, therebyresulting in a threading dislocation at the center of the protrudedportion 11 b. This type-(a+c) threading dislocation is one that has aBurger's vector of ⅓ <11-23> and is concentrated at the center of theprotruded portion 11 a.

The second type of dislocation (type-a dislocation) is as follows. InFIGS. 8A and 8B, dislocation (3) occurs from an interface with thebottom of the recessed portion 11 a, bends in a horizontal direction inthe vicinity of a facet (d), continually extends to the side wall of therecessed portion 11 a and finally disappears. It should be noted thatbending in the horizontal direction does not necessarily occur at thefacet (d). Like the mechanism of the dislocation (3), dislocation (4)bends in a horizontal direction, extends to the vicinity of the centerof the protruded portion 11 b and rises in a vertical direction at theassociated portion of the center of the protruded portion 11 b,resulting in a threading dislocation at the center of the protrudedportion 11 b. The difference from the dislocation (2) resides in theextension in the horizontal direction. Like the mechanism of thedislocation (3), location (5) bends in a horizontal direction andextends to the vicinity of the center of the protruded portion 11 b,whereupon it incidentally extends vertically. This dislocation (5)causes a threading dislocation at the center of the protruded portion 11b. The threading dislocation of this type-a is one that has a Berger'svector of ⅓ <11-20>.

Aside form the type-(a+c) dislocation and type-a dislocation,dislocations freshly threading at the surface of the GaN layer 12 (bothtype-(a+c) dislocation and type-a dislocation) were observed at theassociated portion of the center of the protruded portion 11 b.

Next, the results of estimation of a dislocation density in the GaNlayer 12 are illustrated. As shown in FIG. 9, an angle made between theside wall of the recessed portion 11 a and the main surface of thesapphire substrate 11 is taken as γ and an angle made between aninterface of growth on the protruded portion 11 b and the main surfaceof the sapphire substrate 11 is taken as β, a rate of high densitydefect regions in the GaN layer 12 is expressed as follows:

R=cot β((W _(g)/2)tan α−d)/(½)(W _(t) +W _(g) +d cot γ)

In this case, the dislocation density is estimated asW_(initial)×(R+U(1−R)) wherein U represents a frequency of type-adislocation (c-dislocation) being elevated to the surface of the GaNlayer 12 and is empirically at about 1/10 to 1/100. For instance, when αand β are up to 59 degrees, γ is up to 67 degrees, W_(g) is up to 2.1μm, W_(t) is up to 2 μm, and d is up to 1 μm, R is up to 0.195 whereuponW_(initial) is up to 3×10⁸/cm². When U is up to 1/50, a dislocationdensity is up to 6.3×10⁷/cm².

In FIGS. 10A and 10B, there is shown a sectional TEM photograph of thevicinity of an interface between the sapphire substrate 11 and the GaNlayer 12. FIG. 11 shows a sectional view of the vicinity. FIG. 10Acorresponds to a region surrounded by the dotted line at the protrudedportion 11 b indicated in FIG. 11, and FIG. 10B corresponds to a regionsurrounded by the dotted line at the recessed portion 11 a indicated inFIG. 11. As shown in FIGS. 10A and 10B, the shapes of pits observed atthe side of the sapphire substrate 11 at the interface between thesapphire substrate 11 and the GaN layer 12 differ between the recessedportion 11 a and the protruded portion 11 b. As is particularly shown inFIG. 11, when a width of a pit 13 formed at the recessed portion 11 a istaken as P_(g) and a width of a pit 14 formed at the protruded portion11 b is taken as P_(t), P_(t)>P_(g), typically P_(t)>1.2P_(g). Thereason why the width P_(t) of the pit 14 formed at the protruded portion11 b becomes greater than the width P_(g) of the pit 13 formed at therecessed portion 11 a is that the GaN layer 12 does not grow at theinitial stage of growth at the protruded portion 11 b, so that theprotruded portion 11 b is exposed to NH₃ gas having the etching actionover a long time. In the methods in related art, this would not occur.

FIG. 12A shows a sectional TEM photograph (dark field image) of thevicinity of the recessed portion 11 a and the protruded portion 11 b ofthe sapphire substrate 11, FIG. 12B is a sectional TEM photographenlarging the vicinity of the upper surface of the protruded portion 11b shown in FIG. 12A, and FIG. 12C is a view enlarging the vicinity ofthe bottom surface of the recessed portion 11 a shown in FIG. 12B, inwhich a black portion in each figure indicates the sapphire substrate11. FIG. 13A schematically shows a section of the vicinity of the uppersurface of the protruded portion 11 b shown in FIG. 12B, and thethickness of a region of the GaN layer 12 wherein crystallinity over theprotruded portion 11 b is poor is up to 37 nm. FIG. 13B is schematicallyshows a section of the vicinity of the bottom surface of the recessedportion 11 a shown in FIG. 12C, and the thickness of a region of the GaNlayer 12 wherein crystallinity over the recessed portion 11 a is poorranges from up to 18 nm to up to 56 nm. As will be seen from the above,the thicknesses of the crystallinity-poor regions of the GaN layer 12over the recessed portion 11 a and the protruded portion 11 b differfrom each other. This is because the GaN layer 12 is laterally grownover the protruded portion 11 b. In the methods in related art, nosignificant difference appears.

In FIG. 14, one instance of the results (data indicated by ▪) obtainedby carrying out simulation (lay tracing simulation) of light extractionfrom this GaN light-emitting diode (green emission light-emitting diode)to outside is shown. In FIG. 14, the abscissa indicates an area S of aninclined surface at the side wall of the recessed portion 11 a in casewhere a size range of 20 μm×20 μm is assumed on the sapphire substrate11 and also a ratio of the area S relative to 400 μm² (area ratio of aninclined surface), and the ordinate indicates a light extractionefficiency η. As will be seen from FIG. 14, in order to improve thelight extraction efficiency η, the area S of the inclined surface isincreased to an extent as large as possible. In FIG. 14, there are shownthe results of similar simulation in case where the recessed portions 11a are formed on the sapphire substrate 11 in three directions (e.g.three <1-100> directions that are crystallographically equivalent to oneanother) at intervals of 60 degrees. In this case, the planar shape ofthe protruded portion 11 a is in a triangular form. The results revealthat the light extraction efficiency η is higher in the case where therecessed portions 11 a are formed in the three directions at intervalsof 60 degrees than in the case where the recessed portions 11 a areformed as extending in one direction in a striped form.

With reference to FIG. 15, consideration is again given to maximizationof the area S of the inclined surface so as to increase the lightextraction efficiency η. Assuming a portion of unit length along adirection of the extension of the recessed portion 11 a in FIG. 15, anoccupied area of the recessed portion 11 a and the protruded portion 11b of one cycle on the sapphire substrate 11 is expressed by(W_(t)+W_(g))+d/tan γ, and an area of the inclined surface of the sidewall expressed by d/sin γ. Accordingly, in order to increase the lightextraction efficiency η, it is effective to maximize the ratio of theinclined surface area, (d/sin γ)/((W_(t)+W_(g))+d/tan γ).

FIG. 16 shows a variation in the ratio of the inclined surface area(data indicated by thick solid line) when an angle γ made between theside wall of the recessed portion 11 a and the main surface of thesapphire substrate 11 is changed provided that d=1 μm and W_(t)+W_(g)=4μm. In FIG. 16, the data indicated by a thin solid line indicates adifferential value of the ratio of the inclined surface area. From FIG.16, the ratio of the inclined surface area is at 0.24 when γ=69 degrees.

FIG. 17 shows a variation in the ratio of the inclined surface area(data indicated by thick solid line) when the depth d of the recessedportion 11 a provided that γ=67 degrees and W_(t)+W_(g)=4 μm. In FIG.17, the data indicated by thin solid line indicates a differential valueof the ratio of the inclined surface area. From FIG. 17, the ratio ofthe inclined surface area is at 0.24 under favorable conditions wherethe dislocation density in the GaN layer 12 becomes low (e.g. d=1.66 μm,α=59 degrees and W_(g)=2 μm). In contrast, with d=1 μm, for example, theratio of the inclined surface area is at 0.18.

FIG. 18 shows a variation in the ratio of the inclined surface area(data indicated by thick solid line) when the depth d of the recessedportion 11 a provided that γ=67 degrees and W_(t)+W_(g)=7 μm. In FIG.18, the data indicated by thin solid line indicates a differential valueof the ratio of the inclined surface area. From FIG. 18, the ratio ofinclined surface area is at 0.18 under favorable conditions where thedislocation density in the GaN layer 12 becomes low (e.g. d=1.66 μm,α=59 degrees and W_(g)=2 μm). In contrast, with d=1 μm, for example, theratio of inclined surface area is at 0.12.

Next, consideration is given to the state of growth surface in thevicinity of the active layer 16. In general, when a threading defectexists in a grown layer, a growth pit occurs, thereby causing theflatness of the grown surface to deteriorate as shown in FIG. 19. Ahigher threading dislocation density results in an increased degree ofdeterioration. If a threading dislocation exists in the active layer 16,fluctuations of thickness and composition within the plane takes place,thereby causing inplane inhomogeneity of an emission wavelength andplanar crystal defects such as antiphase boundary defects to occur andthus resulting in a lowering of emission efficiency (i.e. a lowering ofinner quantum efficiency). On the other hand, according to the firstembodiment of the present invention, the threading dislocation densityin the GaN layer 12 is so significantly reduced as stated hereinbefore,and thus, the threading dislocation density in the active layer 16 grownthereon is likewise low. Hence, the lowering of emission efficiencyascribed to the threading dislocation is very small, thereby obtainingan emission efficiency higher than in related art.

The threading dislocations in the GaN layer 12 are concentrated in thevicinity of the center of the protruded portion 11 b of the sapphiresubstrate 11 and are regularly arrayed according to the array of theprotruded portions 11 b. Accordingly, the threading dislocations in theactive layer 16 are regularly arrayed reflectedly. In this way, an areaof portions of the active layer 16 where a flat surface is formedremarkably increases, compared to the case where the threadingdislocation is arranged randomly, thereby leading to an improvedemission efficiency.

Furthermore, where an In component is high in the active layer 16, forexample, and where a grown surface is roughened, a crystal defect wherea planar crystal defect such as an antiphase boundary defect and adislocation are combined is liable to freshly occur, thereby inviting alowering of emission efficiency. In contrast, according to the firstembodiment, the surface flatness of the active layer is remarkablyimproved as set out hereinabove, and such crystal defects are suppressedfrom occurrence and no lowering of emission efficiency takes place.

In order to improve the flatness of the grown surface of the activelayer 16 and reduce planar crystal defects in number, it is effectivethat a barrier layer of the active layer 16 is formed of AlGaN.

As stated hereinabove, according to the first embodiment, since no spaceis formed between the sapphire substrate 11 and the GaN layer 12, alowering of a light extraction efficiency due to the space can beprevented. The threading dislocation in the GaN layer 12 is concentratedin the vicinity of the center of the protruded portion 11 b of thesapphire substrate 11 and a dislocation density in the other portions isas small as about 10⁷/cm² and is thus significantly reduced over a casein related art using a substrate subjected to patterned indentation. Asa consequence, the crystallinity of the GaN semiconductor layer such asthe GaN layer 12 and the active layer 16 grown thereon is significantlyimproved, thereby significantly reducing the non-emission centers innumber. In this way, a GaN light-emitting diode having a very highemission efficiency can be obtained. Additionally, one cycle ofepitaxial growth is sufficient to manufacture the GaN light-emittingdiode and no growth mask is necessary, so that the manufacturingprocedure is simple and the GaN light emitting diode can be made at lowcosts.

Next, a second embodiment of the present invention is described.

In the second embodiment, as shown in FIG. 21A, ion implantation issubjected to a flat sapphire substrate 11 over the entire surfacethereof to amorphousize a surface layer of the sapphire substrate 11,thereby forming an amorphous layer 31. The atom, energy and dosage usedfor the ion implantation are so selected as to be sufficient foramorphousization of the sapphire substrate 11. The atom used for the ionimplantation includes, for example, an inactive atom such as He, Ne, Ar,Kr, Xe or the like, and Si, H, N, Ga or the like. For instance, if Si isused as an atom for ion implantation, an energy for ion implantationranges 10 to 30 keV and a dosage thereof is 1×10¹⁸/cm² or over.

Next, as shown in FIG. 21B, the sapphire substrate 11 formed with theamorphous layer 31 is subjected to patterned indentation to formrecessed portions 11 a and protruded portions 11 b like the firstembodiment.

Thereafter, as shown in FIGS. 21C to 21E, a GaN layer 12 is grown on thesapphire substrate 11, like the first embodiment, in which the amorphouslayer 31 has been formed on the protruded portion 11 b.

Subsequently, the step of growing an n-type GaInN layer 13 andsubsequent steps are advanced to provide a GaN light-emitting diode likethe first embodiment.

According to the second embodiment, advantages similar to the firstembodiment can be obtained.

A third embodiment of the present invention is now described.

In the third embodiment, as shown in FIGS. 22A and 22B, a GaN layer 32is epitaxially grown on a sapphire substrate 11 that has been subjectedto patterned indentation like the first embodiment.

Next, as shown in FIG. 22C, the GaN layer 32 is etched back by the RIEmethod to thinly leave the GaN layer 32 just at the bottom of therecessed portion 11 a of the sapphire substrate 11.

Thereafter, as shown in FIG. 22D, the sapphire substrate 11 is subjectedto ion implantation wholly on the surface thereof to amorphousize asurface layer of the protruded portion 11 b of the sapphire substrate 11to form an amorphous layer 31. At the same time, the GaN layer 32 isalso amorphousized. The atom, energy and dosage used for the ionimplantation are so selected as to be sufficient for amorphousization ofthe GaN layer 32. The atom used for the ion implantation includes, forexample, an inactive atom such as He, Ne, Ar, Kr, Xe or the like, andSi, H, N, Ga or the like. For instance, if Si is used as an atom for ionimplantation, an energy for ion implantation ranges 10 to 30 keV and adosage thereof is 1×10¹⁸/cm² or over.

Next, as shown in FIGS. 22E to 22G, a GaN layer 12 is grown, like thefirst embodiment, over the sapphire substrate 11 in which the amorphouslayer 31 has been formed on the protruded portion 11 b and the amorphousGaN layer 32 has been formed at the bottom of the recessed portion 11 aas illustrated above. It will be noted that the amorphousized GaN layer32 is crystallized during the course of heating to a temperature ofgrowth of the GaN layer 12.

Thereafter, the step of growing an n-type GaInN layer and subsequentsteps are advanced, like the first embodiment, to provide a GaNlight-emitting diode.

According to this third embodiment, advantages similar to the firstembodiment are obtained.

A fourth embodiment of the present invention is described.

In the fourth embodiment, a SiN film 33 is formed, as an amorphouslayer, on a flat sapphire substrate 11 over the entire surface thereof,for example, by a vacuum deposition method, a sputtering method, a CVDmethod or the like in a manner as shown in FIG. 23A. This SiN film 33has a thickness, for example, of 1 nm or over.

Next, as shown in FIG. 23B, the sapphire substrate 11 on which the SiNfilm 33 has been formed is subjected to patterned indentation, forexample, by a RIE method, a powder blasting method, a sand blastingmethod or the like to form recessed portions 11 a and protruded portions11 b as in the first embodiment.

Subsequently, as shown in FIG. 23C, a GaN layer 34 is grown at a lowtemperature, for example, of about 550° C. The thickness of the GaNlayer 34 is, for example, at 200 nm or below. The GaN layer 34 growsseparately on the bottom of each recessed portion 11 a of sapphiresubstrate 11 and also on the SiN film 33 formed on each protrudedportion 11 b.

Next, as shown n FIGS. 23D to 23F, a GaN layer 12 is grown, like thefirst embodiment, over the sapphire substrate 11 wherein the SiN film 33has been formed on the protruded portion 11 b and the GaN layer 34 hasbeen formed at the bottom of the recessed portion 11 a. The GaN layer 34is crystallized during the course of heating to a growth temperature ofthe GaN layer 12. The GaN layer 12 grows on the thus crystallized GaNlayer 34. On the other hand, the GaN layer 34 on the SiN film 33 isevaporated in the course of heating to the growth temperature.

Thereafter, the step of growing an n-type GaInN layer 13 and subsequentsteps are advanced, like the first embodiment, to provide a GaNlight-emitting diode.

According to the fourth embodiment, advantages as in the firstembodiment can be obtained.

A fifth embodiment of the present invention is described.

In the fifth embodiment, as shown in FIG. 24A, a SiN film 35, a SiO₂film 36 and a SiN film 37 are successively formed on a flat sapphiresubstrate 11 on the entire surface thereof, for example, by a vacuumdeposition method, a sputtering method, a CVD method or the like. Thethickness of the SiN films 35, 37 is, for example, at 1 nm or over, andthe thickness of the SiO₂ film 36 is, for example, 10 nm or over.

Next, as shown in FIG. 24B, the sapphire substrate 11 on which the SiNfilm 35, SiO₂ film 36 and SiN film 37 have been formed is subjected topatterned indentation, for example, by a RIE method, a powder blastingmethod, and a sand blasting method or the like to form recessed portions11 a and protruded portions 11 b like the first embodiment.

As shown in FIG. 24C, the SiO₂ film 36 alone is etched by wet etching,for example, with a hydrofluoric acid-based etchant, with its side facebeing slightly retarded along a horizontal direction.

Next, as shown in FIG. 24D, a GaN layer 12 is grown like the firstembodiment. Since the side walls of the SiO₂ film 36 are so horizontallyretarded as mentioned above, the GaN layer 12 is prevented fromdeposition on the side walls of the SiO₂ film 36.

Thereafter, as shown in FIG. 24E, the SiO₂ film 36 is completely removedby wet etching, for example, with a hydrofluoric acid-based etchant,with the result that the SiN film 37 and the GaN layer 34 formed thereonare also removed (lift off).

Subsequently, as shown in FIGS. 24F and 24G, a GaN layer 12 is laterallygrown like the first embodiment.

Like the first embodiment, the step of growing an n-type GaInN layer 13and subsequent steps are advanced to provide a GaN light-emitting diode.

According to the fifth embodiment, advantages as in the first embodimentcan be obtained.

Next, a sixth embodiment is described.

In the sixth embodiment, as shown in FIGS. 25A to 25D, a GaN layer 12 isgrown on a sapphire substrate 11 subjected to patterned indentation,like the first embodiment.

A shown in FIG. 25E, the GaN layer 12 is patterned by use of a RIEmethod or the like to selectively remove a portion thereof over theprotruded portion 11 b wherein threading dislocations are concentrates,thereby permitting the surface of the protruded portion 11 b to beexposed thereat.

As shown in FIGS. 25F and 25G, a GaN layer 37 is laterally grown fromthe GaN layer 12 left on the recessed portion 11 a.

Thereafter, the step of growing an n-type GaInN layer 13 and subsequentsteps are advanced like the first embodiment to provide a GaNlight-emitting diode.

According to this sixth embodiment, advantages as in the firstembodiment can be obtained.

A seventh embodiment of the present invention is next described.

In the seventh embodiment, as shown in FIG. 26A, a GaN layer 38 is grownon a flat sapphire substrate 11.

As shown in FIG. 26B, the GaN layer 38 is subjected patternedindentation to form recessed portions 38 a and protruded portions 38 blike the recessed portions 11 a and protruded portions 11 b of thesapphire substrate 11 of the first embodiment.

Next, a GaN layer 12 is grown over the GaN layer 38 subjected topatterned indentation like the first embodiment.

Thereafter, the step of growing an n-type GaInN layer 13 and subsequentsteps are advanced in the same manner as in the first embodiment toprovide a GaN light-emitting diode.

According to the seventh embodiment, advantages as in the firstembodiment can be obtained.

Next, an eighth embodiment of the present invention is described.

In the eighth embodiment, the first embodiment is repeated until thep-side electrode 21 is formed, with subsequent steps being differenttherefrom. For the formation of the p-side electrode 21, there ispreferably used a technique wherein in order to prevent diffusion of anelectrode material (e.g. Ag or the like), a layer containing Pd isinterposed. Alternatively, in order to prevent occurrence of a failuresuch as by diffusion, in the p-side electrode 21, of Au or Sn from an Auor Sn-containing layer (solder layer, bump or the like) formed on theabove-mentioned layer owing to stress or by application of heat, abarrier metal layer that is grain boundary-free and amorphous in naturemay be used by forming, on the electrode, a layer of a high meltingmetal such as, for example, Ti, W or an alloy thereof, or a nitride ofeach of these metals (e.g. TiN, WN, TiWN or the like). The technique ofinterposing a Pd-containing layer is well known, for example, as aninterposing layer of Pd in the field of metal plating, and the barriermetal materials are well known in Al wiring techniques of Si-basedelectronic devices.

More particularly, as shown in FIG. 27A, after formation of a p-sideelectrode 21, a Ni film 41 is, for example, formed to cover the p-sideelectrode 21 such as by a lift method. Next, although not shown in thefigures, a Pd film is, for example, formed so as to cover the Ni film41, followed by forming a film of a metal nitride such as, for example,TiN, WN, TiWN or the like, to cover the Pd film and further forming afilm of Ti, W, Mo or an alloy thereof, if necessary, to cover thenitride film. Instead of the formation of the Ni film 41, a Pd film maybe formed to cover the p-side electrode 21, followed by forming a filmof TiN, WN, TiWN or the like to cover the Pd film and further forming afilm of Ti, W, Mo or an alloy thereof, if necessary, to cover the filmtherewith.

Next, as shown in FIG. 27B, a resist pattern 42 of a given pattern isformed to cover the Ni film 41 and the upper layers including the Pdfilm by lithography.

Thereafter, as shown in FIG. 27C, etching is carried out, for example,by a RIE method using the resist pattern 42 as a mask to form a mesaportion 22 in the form of a trapezoid in section. The angle made betweenthe inclined surface of the mesa portion 22 and the main surface of thesapphire substrate 11 is set, for example, at about 35 degrees. A λ/4dielectric film wherein λ is an emission wavelength is formed on theinclined surface of the mesa portion 22, if necessary.

Next, as shown in FIG. 27D, an n-side electrode 23 is formed on then-type GaInN layer 13.

Subsequently, as shown in FIG. 27E, a SiO₂ film 43 is formed over theentire surface of the substrate as a passivation film. Where adhesion toan underlying layer, durability and a corrosion resistance in processare taken into account, a SiN film or SiON film may be used in place ofthe SiO₂ film 43.

As shown in FIG. 27F, the SiO₂ film 43 is etched back for reduction inthickness, after which an Al film 44 is formed, as a reflective film, onthe SiO₂ film 43 at the inclined portion of the mesa portion 22. This Alfilm 44 serves to reflect light generated from the active layer 16toward the side of the sapphire substrate 11 thereby improving a lightextraction efficiency. The Al film 44 is so formed as to contact withthe n-side electrode 23 at one end thereof. This is because no space ismade between the Al film 44 and the n-side electrode 23 so as toincrease a reflection of light. Thereafter, a SiO₂ film 43 is againformed to a thickness sufficient for a passivation film.

As shown in FIG. 27G, the portions of the SiO₂ film 43 above the Ni film41 and the n-side electrode 23 are removed by etching to form openings45, 46, thereby causing the Ni film 41 and the n-side electrode 23 to beexposed at these portions.

Next, as shown in FIG. 27H a pad electrode 47 is formed on the Ni film41 at the opening 45, and a pad electrode 48 is formed on the n-sideelectrode 23 at the opening 46.

As shown in FIG. 27I, a bump mask material 49 is formed over the entiresurface of the substrate, after which the bump mask material 49 isremoved by etching a portion thereof above the pad electrode 48 to forman opening 50, at which the pad electrode 48 is exposed.

Next, as shown in FIG. 27J, an Au bump 51 is formed on the pad electrode48 by use of the bump mask material 49, after which the bump maskmaterial 49 is removed. Subsequently, a bump mask material (not shown)is again formed over the entire surface of the substrate, a portion ofthe bump mask material above the pad electrode 47 is removed by etchingto form an opening, at which the pad electrode 47 is exposed. An Au bump52 is formed on the pad electrode 47.

If necessary, the sapphire substrate 11 on which a light-emitting diodestructure has been formed in a manner as set out above is cut or lappedfrom the back side thereof to reduce the thickness of the substrate,followed by scribing the sapphire substrate 11 and forming a bar.Thereafter, the bar is scribed for chipping.

It will be noted that the electrode stacked structure illustrated inFIGS. 27A to 27J is merely an instance. Especially, where the respectiveelectrode layers are plurally stacked, it is necessary how to attainhigh reflectivity by improving adhesion between the p-side electrode 21made of Ag electrodes or the like and other metallic layers, stressdurability and anti-cracking property and to make a low contactresistance and keep the quality of the Ag electrode and the like whiletaking into account suppression of occurrence of a stress ascribed to adifference in coefficient of thermal expansion among the respectivemetal layers accompanied by a rise in device temperature and alsosuppression of diffusion between adjacent metal layers. Thus, it ispossible to make use of Al wiring techniques of Si-based electronicdevices as stated above, if necessary.

A ninth embodiment of the present invention is described.

In the ninth embodiment, the manufacture of light-emitting diodebacklight is illustrated wherein there is used, in addition to the GaNblue light-emitting diode obtained by the method of the first embodimentand the GaN green light-emitting diode, an AlGaInP red light-emittingdiode separately provided for this purpose.

A GaN blue light emitting diode structure is formed on a sapphiresubstrate 11 according to the method of the first embodiment and bumps(not shown) are, respectively, formed on the p-side electrode 21 and then-side electrode 23, followed by chipping to obtain a GaN bluelight-emitting diode in the form of a flip chip. Likewise, a GaN greenlight-emitting diode is obtained in the form of a flip chip. On theother hand, for an AlGaInP red light-emitting diode, an ordinary one isused in the form of a chip, which is obtained by forming an AlGaInPsemiconductor layer on an n-type GaAs substrate to provide a diodestructure, on which a p-side electrode is formed and an n-side electrodeis formed on a back side of the n-type GaAs substrate.

These AlGaInP red light-emitting diode chip, GaN green light-emittingdiode chip and GaN blue light-emitting diode chip are, respectively,mounted on a submount made of AIN or the like, followed by mounting inposition on a substrate such as an Al substrate in such a way that thesubmount is turned downward. This state is shown in FIG. 28A. In FIG.28A, reference numeral 61 indicates a substrate. Likewise, indicated by62 is a submount, by 63 is an AlGaInP red light-emitting diode chip, by64 is a GaN green light-emitting diode chip and by 65 is a GaN bluelight-emitting diode chip. These AlGaInP red light-emitting diode chip63, GaN green light-emitting diode chip 64 and GaN blue light-emittingdiode chip 65, respectively, have a chip size, for example, of 350 μmsquare. The AlGaInP red light-emitting diode chip 63 is so mounted thatan n-side electrode thereof is on the submount 62, and the GaN greenlight-emitting diode chip 64 and the GaN blue light-emitting diode chip65 are, respectively, mounted in such a way that the p-side electrodeand n-side electrode are laid on the submount 62 via bumps. The submount62, on which the AlGaInP red light-emitting diode chip 63 is mounted,has an extraction electrode (not shown) for the n-side electrode thereonin a given pattern. The n-side electrode of the AlGaInP redlight-emitting diode chip 63 is mounted on a given portion of theextraction electrode. The p-side electrode of the AlGaInP redlight-emitting diode chip 63 and a given pad electrode 66 provided onthe substrate 21 are, respectively, bonded with a wire 67 for connectionthereof. Likewise, a wire (not shown) is, respectively, bonded to theextraction electrode at one end thereof and another pad electrodeprovided on the substrate 61, ensuring electric connection thereof. Thesubmount 62 mounting the GaN green light-emitting diode chip 64 thereonhas an extraction electrode for p-side electrode and an extractionelectrode for n-side electrode (both not shown) formed in desiredpatterns, respectively. The p-side electrode and the n-side electrode ofthe GaN green light-emitting diode chip 64 are, respectively, mounted ongiven portions of the extraction electrode for p-side electrode and theextraction electrode for n-side electrode via bumps formed thereon. Oneend of the extraction electrode for p-side electrode of the GaNlight-emitting diode chip 64 and a pad electrode provided on thesubstrate 61 are, respectively, connected with a wire (not shown) bondedthereto, and one end of the extraction electrode for n-side electrodeand a pad electrode provided on the substrate 61 are, respectively,connected with a wire (not shown) bonded thereto. This is same in theGaN blue light emitting diode chip 65.

It will be noted that the submount 62 may not be used, under which theAlGaInP red light-emitting diode chip 63, GaN green light-emitting diodechip 64 and GaN blue light-emitting diode chip 65 are, respectively,mounted directly on an arbitrary printed circuit board having a goodradiation performance, thereby leading to low costs of thelight-emitting diode backlight as a whole.

In practice, such AlGaInP red light-emitting diode chip 63, GaN greenlight-emitting diode chip 64 and GaN blue light-emitting diode chip 65are provided as a unit cell, and a necessary number of the cells arearranged on the substrate 61 in a given pattern. One instance of this isshown in FIG. 29A. Next, as shown in FIG. 28B, the unit cell is pottedwith a transparent resin 68 to cover the cell therewith. The transparentresin 68 is subsequently cured. By the curing, the transparent resin 68is solidified, with which the resin is slightly shrunk (FIG. 28C). Inthis way, there is obtained a light-emitting diode backlight wherein theAlGaInP red light-emitting diode chip 63, GaN green light-emitting diodechip 64 and GaN blue light-emitting diode chip 65 are provided as a unitcell as is particularly shown in FIG. 29B and such cells are arranged inan array on the substrate 61. In this case, the transparent resin 68 isin contact with the back side of the sapphire substrate 11 of the GaNgreen light-emitting diode chip 64 and GaN blue light-emitting diodechip 65, so that a difference in refractive index becomes smaller thanthat of the case where the back side of the sapphire substrate 11 is indirect contact with air. This eventually leads to the fact that lightdischarged to outside by transmission through the sapphire substrate 11is more unlikely to be reflected at the back side of the sapphiresubstrate 11, thereby improving a light extraction efficiency.

This type of light-emitting diode backlight is suitable for use, forexample, as a backlight for liquid crystal panel.

Next, a tenth embodiment of the present invention is described.

In the tenth embodiment, a necessary number of unit cells included ofthe AlGaInP red light-emitting diode chip 63, GaN green light-emittingdiode chip 64 and GaN blue light-emitting diode chip 65 are arranged onthe substrate 61 in a given pattern like the ninth embodiment of thepresent invention. Thereafter, as shown in FIG. 30, a transparent resin69 suited for the AlGaInP red light-emitting diode chip 63 (i.e. higherin transparency relative to light of an emission wavelength of the diodechip) is potted on the AlGaInP light-emitting diode chip 63 to cover theAlGaInP red light-emitting diode chip 63 therewith. Likewise, atransparent resin 70 suited for the GaN green light-emitting diode chip64 is potted on the GaN light-emitting diode chip 64 to cover the GaNgreen light-emitting diode chip 64 therewith, and a transparent resin 71suited for the GaN blue light-emitting diode chip 65 is potted on theGaN blue light-emitting diode chip 65 to cover the GaN bluelight-emitting diode chip 65 therewith. Thereafter, the transparentresins 69 to 71 are cured, respectively. By the curing, the transparentresins 69 to 71 are solidified and slightly shrunk as a result of thesolidification. In this way, three can be obtained a light emittingdiode backlight wherein a number of cells, each made of the AlGaInP redlight-emitting diode chip 63, GaN green light-emitting diode chip 64 andGaN blue light-emitting diode chip 65, are arranged in an array on thesubstrate 61. In this case, the transparent resins 70, 71 are in contactwith the back side of the sapphire substrate 11 of the GaN greenlight-emitting diode chip 64 and GaN blue light-emitting diode chip 65,so that a difference in refractive index becomes smaller than that ofthe case where the back side of the sapphire substrate 11 is in directcontact with air. This eventually leads to the fact that lightdischarged to outside by transmission through the sapphire substrate 11is more unlikely to be reflected at the back side of the sapphiresubstrate 11, thereby improving a light extraction efficiency.

This type of light-emitting diode backlight is suitable for use, forexample, as a backlight for liquid crystal panel.

Next, an eleventh embodiment of the present invention is described.

In the eleventh embodiment, a GaN light-emitting diode structure isformed on the sapphire substrate 11 according to the procedure of thefirst embodiment, and bumps (not shown) are formed on the p-sideelectrode 21 and the n-side electrode 23, respectively. Thereafter, thesapphire substrate 11 is scribed into a square piece of a given size. Inthis way, as shown in FIG. 31, an integrated GaN light-emitting diodehaving striped emission portions can be obtained. In this case, then-side electrode 23 is formed to surround a striped mesa portion 22therewith. As shown in FIG. 32, the integrated GaN light-emitting diodeis mounted on a submount 69 made of AIN or the like. The submount 69 hasan extraction electrode for p-side electrode and an extraction electrodefor n-side electrode (both not shown) formed in give patterns,respectively, on which solder bumps 70, 71 are formed. The integratedGaN light-emitting diode is so mounted that the p-side electrode 21 isplaced on the solder 70 and the n-side electrode 23 is on the solder 71,followed by melting the solders 70, 71 for bonding.

Next, a twelfth embodiment of the present invention is described.

In the twelfth embodiment, the manufacture of a light source cell unitis illustrated, in which there is used, aside from the GaN bluelight-emitting diode and the GaN green light-emitting diode obtained inthe procedure of the first embodiment, a AlGaInP red light-emittingdiode made separately.

As shown in FIG. 33A, a necessary number of cells 81, each of whichincludes the AlGaInP red light-emitting diode chip 63, GaN greenlight-emitting diode chip 64 and GaN blue light-emitting diode chip 65,each diode being at least one in number, and these diodes are arrangedin a given pattern, are arranged on a printed circuit board 82 in agiven pattern. In this instance, individual cells 81 contain one AlGaInPred light-emitting diode chip 63, one GaN green light-emitting diodechip 64 and one GaN blue light-emitting diode chip 65, which are locatedat apexes of a triangle. FIG. 33B shows an enlarged cell 81. Thedistance a between the AlGaInP red light-emitting diode chip 63, GaNgreen light-emitting diode chip 64 and GaN blue light-emitting diodechip 65 in the respective cells 81 is, for example, at 4 mm although notlimited thereto. The distance b if cells 81 is, for example, at 30 mmalthough not limited. For the printed circuit board 82, a FR4 (flameretardant type 4) substrate, a metal core substrate or the like can beused although not limited thereto, and other types of substrates mayalso be used provided that they are printed board substrates having aradiation performance. Like the ninth embodiment, a transparent resin 68is potted to cover the individual cells 81 therewith. Alternatively,like the tenth embodiment, a transparent resin 69 is potted to cover theAlGaInP red light-emitting diode chip 63, a transparent resin 70 ispotted to cover the GaN green light-emitting diode chip 64, and atransparent resin 71 is potted to cover the GaN blue light-emittingdiode chip 65. In this manner, there can be obtained light source cellunit wherein the cells 81 each made of the AlGaInP red light-emittingdiode chip 63, the GaN green light-emitting diode chip 64 and the GaNblue light-emitting diode chip 65 are arranged over the printed circuitboard 82.

Specific examples of the arrangement of the cells 81 on the printedcircuit board 82 are shown in FIGS. 34A and 34B. The instance shown inFIG. 34A is a 4×3 two-dimensional array of the cells 81 and the instanceshown in FIG. 34B is a 6×2 two-dimensional array of the cells 81.

FIG. 35 shows an instance of other type of array of the cells 81. Inthis instance, the cell 81 includes one AlGaInP red light-emitting diodechip 63, two GaN green light-emitting diode chips 64 and one GaN bluelight-emitting diode chip 65, which are arrayed, for example, at apexesof a square. The two GaN green light-emitting diode chips 64 are arrayedat apexes located at opposite ends of one of diagonal lines of thesquare, and the AlGaInP red light-emitting diode chip 63 and the GaNblue light-emitting diode chip 65 are arrayed at apexes located atopposite ends of the other diagonal line.

When this type of light source unit is arranged singly or plurally, alight-emitting diode backlight can be suitably used, for example, as abacklight for liquid crystal panel.

The embodiments of the present invention have been specificallyillustrated hereinabove, and the present invention should not beconstrued as limiting to these embodiments. Many variations based on thetechnical concept of the present invention may be possible.

For instance, the values, materials, structures, shapes, substrates,starting materials, processes, and the extension direction of recessedportion 11 a illustrated in the first to twelfth embodiments of thepresent invention are merely examples. If necessary, values, materials,structures, shapes, substrates, starting materials, processes and thelike that are different from those illustrated before may be used.

Further, in the first to twelfth embodiments of the present invention,for example, the conduction types of the p-type GaN semiconductor layerand the n-type GaN semiconductor layer may be reversed each other. Inaddition, a SiC substrate, a Si substrate and other types of substratesmay be used in placed of the sapphire substrate 11, for example.

The extension direction of the recessed portion 11 a may not be a<1-100> direction of the GaN layer 12, but also a <11-20> direction ofthe GaN layer 12.

If necessary, two or more of the first to twelfth embodiments may becombined.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

1. A light-emitting diode, comprising: a substrate having at least one recessed portion on one main surface; a sixth nitride-based III-V group compound semiconductor layer grown on the substrate without forming a space in the recessed portion; and a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type formed over the sixth nitride-based III-V group compound semiconductor layer, wherein, a dislocation occurring, in the sixth nitride-based III-V group compound semiconductor layer, from an interface with a bottom surface of the recessed portion in a direction vertical to the one main surface arrives at an inclined face or its vicinity of a triangle having the bottom surface of the recessed portion as a base and bends in a direction parallel to the one main surface.
 2. A light-emitting diode, comprising: a substrate having at least one recessed portion on one main surface; a sixth nitride-based III-V group compound semiconductor layer grown on the substrate without forming a space in the recessed portion; and a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type formed over the sixth nitride-based III-V group compound semiconductor layer, wherein, a first pit having a first width is formed in the substrate at a bottom of the recessed portion and a second pit having a second width larger than the first width is formed in the substrate at a bottom of the recessed portion.
 3. An integrated light-emitting diode having a plurality of light-emitting diodes integrated, at least one light-emitting diode comprising: a substrate having at least one recessed portion on one main surface; a sixth nitride-based III-V group compound semiconductor layer grown on the substrate without forming a space in the recessed portion; and a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type formed over the sixth nitride-based III-V group compound semiconductor layer, wherein, a dislocation occurring, in the sixth nitride-based III-V group compound semiconductor layer, from an interface with a bottom surface of the recessed portion in a direction vertical to the one main surface arrives at an inclined face or its vicinity of a triangle having the bottom surface of the recessed portion as a base and bends in a direction parallel to the one main surface.
 4. A light source cell unit which comprises a printed circuit board and a plurality of cells formed on the printed circuit board, each cell containing at least one red light-emitting diode, at least one green light-emitting diode and at least one blue light-emitting diode, at least one of the red light-emitting diode, the green light-emitting diode and the blue light-emitting diode including: a substrate having at least one recessed portion on one main surface; a sixth nitride-based III-V group compound semiconductor layer grown on the substrate without forming a space in the recessed portion; and a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type formed over the sixth nitride-based III-V group compound semiconductor layer, wherein, a dislocation occurring from an interface with a bottom surface of the recessed portion in a direction vertical to the one main surface in the sixth nitride-based III-V group compound semiconductor layer arrives at an inclined face or its vicinity of a triangle having the bottom surface of the recessed portion as a base and bends in a direction parallel to the one main surface.
 5. A light-emitting diode backlight which comprises plural red light-emitting diode, plural green light-emitting diode and plural blue light-emitting diode arranged in pattern, at least one of the red light-emitting diode, the green light-emitting diode and the blue light-emitting diode including: a substrate having at least one recessed portion on one main surface; a sixth nitride-based III-V group compound semiconductor layer grown on the substrate without forming a space in the recessed portion; and a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type formed over the sixth nitride-based III-V group compound semiconductor layer, wherein, a dislocation occurring, in the sixth nitride-based III-V group compound semiconductor layer, from an interface with a bottom surface of the recessed portion in a direction vertical to the one main surface arrives at an inclined face or its vicinity of a triangle having the bottom surface of the recessed portion as a base and bends in a direction parallel to the one main surface.
 6. A light-emitting diode display which comprises plural red light-emitting diodes, plural green light-emitting diodes and plural blue light-emitting diodes arranged in pattern, at least one of the red light-emitting diode, the green light-emitting diode and the blue light-emitting diode including: a substrate having at least one recessed portion on one main surface; a sixth nitride-based III-V group compound semiconductor layer grown on the substrate without forming a space in the recessed portion; and a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type formed over the sixth nitride-based III-V group compound semiconductor layer, wherein, a dislocation occurring, in the sixth nitride-based III-V group compound semiconductor layer, from an interface with a bottom surface of the recessed portion in a direction vertical to the one main surface arrives at an inclined face or its vicinity of a triangle having the bottom surface of the recessed portion as a base and bends in a direction parallel to the one main surface.
 7. An electronic device having at least one light-emitting diode, at least the one light-emitting diode comprising: a substrate having at least one recessed portion on one main surface; a sixth nitride-based III-V group compound semiconductor layer grown on the substrate without forming a space in the recessed portion; and a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type formed over the sixth nitride-based III-V group compound semiconductor layer, wherein, a dislocation occurring, in the sixth nitride-based III-V group compound semiconductor layer, from an interface with a bottom surface of the recessed portion in a direction vertical to the one main surface arrives at an inclined face or its vicinity of a triangle having the bottom surface of the recessed portion as a base and bends in a direction parallel to the one main surface. 